In this paper we report on the modeling and simulation of tunneling current in MOS devices including quantum mechanical effects. The simulation model features an original scheme for the self-consistent solution of Poisson and Schrodinger equations and it is used for the extraction of the oxide thickness, by fitting CV curves, and the calculation of the tunneling current. Simulations and experiments are compared for different device types and oxide thicknesses (1.5-6.5 nm) showing good agreement and pointing out the importance of quantum mechanical modeling and the presence of many tunneling mechanisms in ultra-thin oxide MOS devices.

A first-order investigation of the transport and energy-loss processes in silicon dioxide is worked out in the frame of the Spherical-Harmonics solution of the Boltzmann Transport Equation. The SiO₂ conduction band is treated as a single-valley spherical and parabolic band. The relevant scattering mechanisms are modeled consistently: both the polar and nonpolar electron-phonon scattering mechanisms are considered. The scattering rates for each contribution are analyzed in comparison with Monte Carlo data. A number of macroscopic transport properties of electrons in SiO₂ are worked out in the steady-state regime for a homogeneous bulk structure. The investigation shows a good agreement in comparison with experiments in the low-field regime and for different temperatures.

We compare the numerical results for electron direct tunneling currents for single gate oxides, ON- and ONO-structures. We demonstrate that stacked dielectrics can keep the tunneling currents a few orders of magnitude lower than electrostatically equivalent single oxides. We also discuss the impact of gate material and of the modeling of electron transport in silicon.

The gate oxide of sub-0.1 µm MOSFETs channel length is expected to be reduced beyond 3 nm in spite of an increasing direct tunneling gate current. As tunnel injection modeling into SiO₂ is expected to depend on the electron transport model adopted for the device description, a critical comparison is made in this paper between gate currents obtained from simulators based on Drift-Diffusion, Energy-Balance, and Monte Carlo models. The studied device is a 0.07 µm channel length n-MOSFET with 1.5 nm thick gate oxide. It is shown that positive drain voltage is responsible for two opposite effects on DT leakage: a carrier heating and a potential barrier hardening along the channel. It is proved by a careful study of Monte Carlo microscopic quantities that, contrary to what holds for thicker gate oxide transistors, the balance is favorable to the potential barrier effect. Injection into SiO₂ is then dominated by near-thermal carriers injected at the channel beginning. For this reason, the gate current decreases when increasing the drain bias, with the maximum leakage obtained for (V_gs=V_dd, V_ds=0), and a correct agreement is obtained between the Drift-Diffusion, Energy-Balance, and Monte Carlo approaches of gate current calculation, in spite of very different physical descriptions of transport at the microscopic level.

We investigate the intrinsic current fluctuations in small Si-MOSFETs via the Monte Carlo device simulation. It is demonstrated that the temporal fluctuation of the drain current in Si-MOSFETs attains a significant fraction of the averaged drain current when the device width is scaled down to the deep sub-µm regime. This is caused by the drastic decrease in the number of channel electrons. This finding holds true whenever the device width is reduced to deep sub-µm, regardless of the channel length. Most importantly, current fluctuation is associated with the quasi-equilibrium thermal noise in the heavily-doped source and drain regions, whereas its magnitude with respect to the averaged drain current is directly related to the number of channel electrons underneath the gate.

A Schottky contact model was implemented as a boundary condition for Monte Carlo device simulations. Unlike the ideal ohmic contact, the thermal equilibrium is unnecessary around the Schottky contact. Therefore, the wide region with high impurity concentration around the contact is not required to maintain the thermal equilibrium, which means that it is possible to avoid assigning a lot of particles to the low-field region. The validity of the present boundary condition for contacts was verified by simulating a rectifying characteristic of a Schottky barrier diode. As an application example using the present contact model, we simulated transport in n⁺nn⁺ structures with sub-0.1 µm channel lengths. We observed direction dependence of the electron velocity dispersion, which indicates that the direction dependence of the diffusion constant or the carrier temperature should be taken into account in the hydrodynamic simulation for sub-0.1 µm devices.

An approach for analysis of the small signal response of the carriers in semiconductors is presented. The integro-differential equation, describing the phenomenon in the time domain is transformed into a Fredholm integral equation of the second kind. The response of the carrier system to a small signal of a general time dependence can be calculated by the knowledge of the response to an impulse signal, defined by a delta function in time. For an impulse signal, the obtained integral equation resembles the basic structure of the integral form of the time dependent (evolution) Boltzmann equation. Due to this similarity a physical model of the impulse response process is developed. The model explains the response to an impulse signal in terms of a relaxation process of two carrier ensembles, governed by a Boltzmann equation. A Monte-Carlo method is developed which consists of algorithms for modeling the initial distribution of the two ensembles. The numerical Monte-Carlo theory for evaluation of integrals is applied. The subsequent relaxation process can be simulated by the standard algorithms for solving the Boltzmann equation. The presented simulation results for Si and GaAs electrons serve as a test of the Monte-Carlo method and demonstrate that the physical model can be used for explanation of the small signal response process.

A comprehensive analysis methodology allowing investigation of the RF performance of Si and strained Si:SiGe MOSFETs is presented. It is based on transient ensemble Monte Carlo simulation which correctly describes device transport, and employs a finite element solver to account for complex device geometries. Transfer characteristics and figures of merit for a number of existing and proposed RF MOSFETs are discussed.

This work presents the first comprehensive full-band Monte Carlo model for the simulation of silicon/silicon-germanium devices with arbitrary germanium profiles. The model includes a new CPU and memory efficient method for the discretization of the Brillouin zone based on adaptive nonuniform tetrahedral grids and a very efficient method for transfers through heterointerfaces in the case of irregular -space grids. The feasibility of the FB-MC simulation is demonstrated by application to an industrial HBT with a graded germanium profile and different aspects of the microscopic carrier transport are discussed. Internal distributions of the transistor are calculated with a very low noise level and high efficiency allowing a detailed investigation of the device behavior.

Simulation of multi-band quantum transport based on a non-equilibrium Green's functions is presented in resonant tunneling diodes (RTD's), where realistic band structures and space charge effect are taken into account. To include realistic band structure, we have used a multi-band (MB) tight binding method with an sp³s^* hybridization. As a result, we have found that the multiband nature significantly changes the results of conventional RTD simulations specifically for the case with indirect-gap barriers.

We present calculations of the linear-response conductance of a SiGe based single-electron transistor (SET). The conductance and the discrete charging of the quantum dot are calculated by free-energy minimization. The free-energy calculation takes the discrete level-spectrum as well as complex many-body interactions into account. The tunneling rates for tunneling through the source and lead barrier are calculated using Bardeen's transfer Hamiltonian formalism. The tunneling matrix elements are calculated for transitions between the zero-dimensional states in the quantum dot and the lowest subband in the one-dimensional constriction. We compare the results for the conductance peaks with those from calculations with a constant tunneling rate where the shape of the peaks is only due to energetic arguments.

Silicon self-interstitial atom diffusion and implantation induced damage were studied by using molecular dynamics methods. The diffusion coefficient of interstitial silicon was calculated using molecular dynamics method based on the Stillinger-Weber potential. A comparison was made between the calculation method based on the Einstein relationship and the method based on a hopping analysis. For interstitial silicon diffusion, atomic site exchanges to the lattice atoms occur, and thus the total displacement-based calculation underestimates the ideal value of the diffusivity of the interstitial silicon. In addition with calculating the diffusion constant, we also identified its migration pathway and barrier energy in the case of Stillinger-Weber potential. Through a study of molecular dynamics calculation for the arsenic ion implantation process, it was found that the damage self-recovering process depends on the extent of damage. That is, damage caused by a single large impact easily disappears. In contrast, the damage leaves significant defects when two large impacts in succession cause an overlapped damage region.

This paper reports a Monte Carlo calculation of the bimolecular reaction of arsenic precipitation. As the accuracy of the numerical solution for the coupled rate equations strongly depends on the size of grid spacing, it is necessary to choose adequate number of rate equations in order to understand the behavior of the extended defects. Therefore, we developed a general kinetic Monte Carlo model for the extended defects, which explicitly takes the time evolution of the size density of the extended defects into account. The Monte Carlo calculation exhibits a quantitative agreement with the experimental data for deactivation, and successfully reproduces the rapid deactivation at the beginning phase followed by slow deactivation in the subsequent steps.

The high accuracy which is necessary for modern process simulation often requires the use of Monte-Carlo ion implantation simulation methods with the disadvantage of very long simulation times especially for three-dimensional applications. In this work a new method for an accurate and CPU time efficient three-dimensional simulation of ion implantation is suggested. The approach is based on a combination of the algorithmic capabilities of a fast analytical and the Monte-Carlo simulation method.

This paper reports the implementation in three dimensions (3D) of diffusion models for low dose implanted dopants in silicon and the various numerical issues associated with it. In order to allow the end-users to choose between high accuracy or small calculation time, a conventional and 5-species diffusion models have been implemented in the 3D module DIFOX-3D belonging to the PROMPT plateform. By comparison with one and two-dimensional (1D and 2D) simulations performed with IMPACT-4, where calibrated models exist, the validity of this 3D models have been checked. Finally, the results obtained for a 3-dimensional simulation of a rapid thermal annealing step involved in the manufacturing of a MOS transistor are presented what show the capability of this module to handle the optimization of real devices.

The application of Technology CAD simulations for development of IC processes in foundry is presented. Examples include device design, Flash cell design and optical proximity correction for SRAM cell. The challenges of using TCAD tools in the IC foundry is also discussed.

This paper reports the application results of the state-of-the-art advanced process/device modeling to the 0.13 [µm] CMOS design solution. It has been demonstrated that the S/D-extension junction depth, the well profile, the channel profile and the drive current of the 0.13 [µm] CMOS can be predicted with reasonable accuracy. Further model improvement is required to predict the ΔL and the Vt-Lg characteristics of the devices with the tilted pocket I/I more accurately. It is quite beneficial to construct several design maps by using the state-of-the-art advanced TCAD in a 'carpet bombing' way in the early stage of the development of new generation CMOS.

In this paper, we propose an effective SOI yield engineering methodology by practical usage of 2D simulations. Process design for systematic yield of Fully-Depleted SOI MOSFET requires specific consideration of floating-body effects and parasitic channel leakage currents. The influence of varied SOI layer thickness to such phenomena is also complicated and substantial. Instead of time-consuming 3D simulators, 2D simulators are used to optimize the process considering these effects in acceptable turn around time. Our methodology is more effective in future scaled-down process with decreased SOI layer thickness.

In MPU and ASIC design with 0.2 µm BiCMOS LSIs, it is well known that interconnect delay becomes one of the key data to ensure high operating frequency. To verify the whole path delay accurately, one needs to create huge delay and waveform libraries which reflect updated process and interconnect structure as well as device performance. Because of the necessity for more than 100 k times of circuit simulation to create the libraries, it was impossible to update the library quickly including process variation effects. In this paper, we have proposed a realistic new method to generate the libraries on the basis of RSM (Response Surface Method). In application for a BiCMOS ASIC process, we have verified that the new method has achieved the reduction of library creation time to 1/100 within the delay error of 3%. This technique can be used in our TCAD and DA framework, which gives a predictive TCAD generation of delay libraries in concurrent ASIC system and process development.

We present a simulation system which meets the requirements for practical application of inverse modeling in a professional environment. A tool interface for the integration of arbitrary simulation tools at the user level is introduced and a methodology for the formation of simulation networks is described. A Levenberg-Marquardt optimizer automates the inverse modeling procedure. Strategies for the efficient execution of simulation tools are discussed. An example demonstrates the extraction of doping profile information on the basis of electrical measurements.

As scaling has been continued more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 µm as proposed in SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multi-million transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. And advanced topics of interconnect modeling in deep submicron are reviewed; statistical interconnect modeling.

A circuit-level electrothermal simulator, MICS (MItsubishi Circuit Simulator), is presented with parasitic bipolar transistor action and lattice heating taken into account. Diffusion capacitance in parasitic bipolar transistors is introduced to cover turn-on behavior under short rise-time current. Device temperatures are simulated from calculated electrical characteristics and the closed-form solution of the heat transfer equation. Simulation results show that this tool is valuable in evaluating electrostatic discharge (ESD) robustness in integrated circuits (ICs).

A BSIM3v3 based ferroelectric memory field effect transistor (FEMFET) compact model for circuit simulation is presented. Its analytical approach is based on the MOS capacitor equations taking into account the influence of a ferroelectric polarization. The hysteresis behavior of the gate ferroelectric has been modeled by using the distribution function integral method (DFIM). The parameters for the presented simulations were extracted by measurements on MIS and MFIS structures.

We present several challenging gridding problems for multi-dimensional device and process simulation and discuss how new strategies might contribute to their solution. Formulating grid quality requirements for the standard Scharfetter-Gummel box method discretization in device simulation, we demonstrate how the offsetting techniques compares with quadtree grid generation methods and how they apply to modern device designs. Further we present a grid adaptation approach which respects the grid quality criteria and touch upon the main adaptation difficulties within device simulation. For the 3D moving boundary grids in process simulation we present a new algorithm.

Appropriate meshes are crucial for accurate and efficient 3D process simulation. In this paper, we present a set of tools operating on surface and interface triangulations. These tools allow the improvement of the accuracy of interfaces, the reduction of the number of triangles, and the removal of obtuse not coplanarily compensated triangles. The first tool is used within integrated topography simulation environments based on different data structures, e.g. cell-based and segment-based. The latter two are particularly important for providing appropriate input to mesh generation for 3D process simulation.

A three-dimensional mesh generation method in which triangulation of the domain boundary is performed first is desirable since such a method would make it easier to achieve the requirements for the mesh around the boundary. We have developed a mesh generator for a 3D device simulator based on this approach. This mesh generator recursively subdivides a box that includes the whole domain into smaller boxes (cells), a method known as the octree technique. Although our mesh generator is similar to previously reported mesh generators in the sense that it utilizes recursive subdivision of elements, its major difference is that it constructs a triangular mesh upon boundaries of the domain first and this triangular mesh is not changed in the following processes. In order to generate a mesh suitable for the control volume method, a "forbidden region" is introduced and mesh points in the domain are allocated outside of this region. Since the triangular mesh is determined prior to tessellation of the domain, this method is suitable for handling layered mesh along the boundary, which is often necessary to estimate large flows parallel to the boundary precisely. A simple method to provide a layered mesh for a planar boundary is incorporated into the mesh generator. This mesh generator is integrated within our in-house three-dimensional device simulation system. The simulator's practicality is demonstrated through analysis of the reverse narrow channel effect for MOSFETs with LOCOS isolation structures. The effect of protection of the boundary by the layered mesh is also examined by calculating I_d-V_g characteristics of a MOSFET with an oblique Si surface, and it is shown that protection of the whole surface of the channel region is necessary to estimate drain current correctly.

A surface extraction algorithm with NURBS has been developed for the mesh generation from the scattered data after a cell-based simulation. The triangulation of a surface is initiated with a step of describing the geometry along the polygonal boundary with multiple points. In this work, an NURBS surface can be generated with scattered data for each polygonal surface by employing a multilevel B-spline surface approximation. The NURBS mesh in accordance with our algorithm excellently represents the surface evolution of the topography on the wafer. A dynamically allocated topography model, so-called cell advancing model, is proposed to resolve an extensive memory requirement for the numerical simulation of a complicated structure on the wafer. A concave cylindrical DRAM cell capacitor was chosen to test the capability of our model. A set of capacitance present in the cell capacitor and interconnects was calculated with three-dimensional tetrahedral meshes generated from the NURBS surface on CRAY T3E supercomputer. A total of 5,475,600 (130 156 270) cells was employed for the simulation of semiconductor regions comprising four DRAM cell capacitors with a dimension of 1.3 µm 1.56 µm 2.7 µm . The size of the required memory is about 22 Mbytes and the simulation time is 64,082 seconds. The number of nodes for the FEM calculation was 70,078 with 395,064 tetrahedrons.