The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.

The delay time component (τs) of an InGaAs MOSFET caused by dynamic source resistance is discussed. On the basis of the relationship between the current density (J) and the dynamic source resistance (rs), the value of rs is proportional to 1/J with some offset at low current densities, whereas the offset becomes smaller in a region of high current density. The value of τs depends on the current in a way similar to rs. Because the offset in the high-current-density region is proportional to the square root of the effective mass, an InGaAs MOSFET with a small mass has a shorter rs than a Si MOSFET.

A Schottky contact model was implemented as a boundary condition for Monte Carlo device simulations. Unlike the ideal ohmic contact, the thermal equilibrium is unnecessary around the Schottky contact. Therefore, the wide region with high impurity concentration around the contact is not required to maintain the thermal equilibrium, which means that it is possible to avoid assigning a lot of particles to the low-field region. The validity of the present boundary condition for contacts was verified by simulating a rectifying characteristic of a Schottky barrier diode. As an application example using the present contact model, we simulated transport in n+nn+ structures with sub-0.1 µm channel lengths. We observed direction dependence of the electron velocity dispersion, which indicates that the direction dependence of the diffusion constant or the carrier temperature should be taken into account in the hydrodynamic simulation for sub-0.1 µm devices.