In this paper, we report the fabrication and device characteristics of InP/InGaAs double heterojunction bipolar transistors (DHBTs) with buried SiO2 wires. The SiO2 wires were buried in the collector and subcollector layers by metalorganic chemical vapor deposition toward reduction of the base-collector capacitance under the base electrode. A current gain of 22 was obtained at an emitter current density of 1.25 MA/cm2 for a DHBT with an emitter width of 400 nm. The DC characteristics of DHBTs with buried SiO2 wires were the same as those of DHBTs without buried SiO2 wires on the same substrate. A current gain cutoff frequency (fT) of 213 GHz and a maximum oscillation frequency (fmax) of 100 GHz were obtained at an emitter current density of 725 kA/cm2.

1.55µm GaInAsP/InP BH lasers with multiple p-n current blocking layer were fabricated entirely by low-pressure OMVPE. The undercut portions were filled in a manner similar to mass transport process. The laser shows a threshold current of 48 mA at 300 K under CW operation.

Gain and loss coefficients were determined for GaInAsP/InP (λg1.5 µm) grown by OMVPE from lasing characteristics. Crystal quality of OMVPE GaInAsP/InP was found to be substantially the same as those grown be LPE. Absorption losses of the quaternary active and the binary InP layers were estimated separately.

With the aim of achieving heterogeneous integration of compound semiconductors with silicon technology, the fabrication of an InP/InGaAs transferred-substrate HBT (TS-HBT) on a Si substrate is reported. A current gain of 70 and a maximum current density of 12.3 mA/µm2 were confirmed in a TS-HBT with a 340-nm-wide emitter. From microwave characteristics of the TS-HBT obtained after de-embedding, a cutoff frequency (fT) of 510 GHz and a 26% reduction of the base-collector capacitance were estimated. However, the observed fT was too high for an HBT with a 150-nm-thick collector. This discrepancy can be explained by the error in de-embedding, because an open pad is observed to have large capacitance and strong frequency dependence due to the conductivity of the Si substrate.

Fabrication of GaInAsP/InP heterostructure lasers for 1.5 µm wavelength region by organometallic vapor phase epitaxy are discussed. Results of growth conditions, which were experimentally found important to obtain the low threshold current density (1 kA/cm2) comparable with LPE at 1.5 µm lasing oscillation are reported, such as gas switching at hetero-interfaces, maintenance of constant temperature over the growth of all layers, selection of carrier gas and doping conditions. Furthermore, OMVPE device techniques for buried heterostructure laser operating at CW condition are described. Fabrications and characterization of quantum well structure are also reported.

The feasibility of a new transistor structure was demonstrated through an experimental observation of current gain and voltage gain. The proposed transistor structure is a hot electron transistor without a base layer to minimize scattering. Electron emission from the emitter is controlled using positively biased Schottky gate electrodes located on both sides of the emitter mesa. Monte Carlo simulation shows an estimated delay time of 0.17 ps and low gate leakage current with open-circuit voltage gain over unity. To confirm the basic operation, the device with a 25 nm wide emitter was fabricated. To obtain saturated current-voltage characteristics, the emitter was surrounded by gates and parasitic regions were eliminated by electron beam lithography. The observed open-circuit voltage gain was 25. To obtain a low leakage current, an electron energy smaller than the Γ-L separation was necessary to maintain the ballistic nature of the electron. When the gate-emitter voltage was 0.8 V, the gate leakage current was only 4% of the collector current. Thus voltage amplication and current amplification were confirmed simultaneously.

In this study, simulations are performed to design an optimal device for thinning the GaN channel layer on the semi-insulating layer in HEMT. When the gate length is 50nm, the thickness of the undoped channel must be thinner than 300nm to observe the off state. When the GaN channel layer is an Fe-doped, an on/off ratio of ~300 can be achieved even with a gate length of 25nm, although the transconductance is slightly reduced.

GaInAs/InP MOSFETs were fabricated by organometallic vapor phase epitaxy (OMVPE) for the first time to obtain an effective channel mobility of 900 cm2/Vs comparable to the best data by other growth techniques. For the MOS structure, a native oxide layer was formed by low-temperature (220) oxidation technique using water. Due to potentially high uniformity, OMVPE MOSFET technique could be very attractive in the optoelectronic integrated circuits(OEIC) for optical communication.

In this paper, we describe the effect of p-regions on the I-V kink in GaAs FETs. A kink-free p-pocket-type self-aligned gate GaAs MESFET (PP-MESFET), which does not include p-regions under the channel, has been analyzed and compared with a conventional buried-p-type self-aligned gate GaAs MESFET (BP-MESFET) using two-dimensional device simulation. The relation between the I-V kink and the layout of p-regions has been demonstrated by numerical simulation for the first time. For both the BP-MESFET and PP-MESFET, impact ionization produces holes in high-field regions. The holes accumulate under the channel, widen the channel, and cause an abrupt increase in drain current in turn in the BP-MESFET. On the other hand, in the PP-MESFET, holes generated in the high-field region are transported to the source region easily over the lower barrier owing to the absence of p-regions under the channel. Holes do not accumulate under the channel, leading to kink-free I-V characteristics of the PP-MESFET. P-regions should be located so as not to cause the accumulation of holes in GaAs FETs where p-regions are required for high-frequency performance.

We investigated collector current spreading in InGaAs single heterojunction bipolar transistors (SHBTs) having a collector thickness of 75 nm. SHBTs were fabricated with three different emitter widths -- 200, 400, and 600 nm -- and the highest cutoff frequency that was obtained was 468 GHz. The relationship between the current density at the highest cutoff frequency and the emitter width could not be used to estimate the current spreading because it was independent of the collector-base voltage. However, the relationship between the current density with the increase in the total collector-base capacitance and the emitter width indicates current spreading in the collector. The current spreading was estimated to be approximately 90 nm.

In this paper, we report a reduction in the access resistance of InP/InGaAs composite-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) with a back-source electrode. The source region has two electrodes. The source electrode on the surface side is connected to the channel through a doped layer and supplies the electrons. The back-source electrode is constructed under the channel layer and is insulated from the doped layer in order to avoid current leakage. The function of the back-source electrode is to increase the carrier concentration in the channel layer of the source region. In the simulation, the electron density in the channel layer is almost doubled by the effect of the back-source voltage. The fabricated III-V MOSFET has a channel length of 6 µm. A 6% increase in the maximum drain current density (Id) and a 6.8% increase in the transconductance (gm) (Vd = 2 V) are observed. The increase in the carrier density in the channel is estimated to be 20% when the applied voltage of the back-source electrode is 6 V.

In this paper, we report the reduction in the base-collector capacitance (CBC) of InP/InGaAs double heterojunction bipolar transistors with buried SiO2 wires (BG-HBT). In a previous trial, we could not confirm a clear difference between the CBC of the conventional HBT and that of the BG-HBT because the subcollector layer was thicker than expected. In this study, the interface between the collector and the subcollector was shifted to the middle of the SiO2 wires by adjusting the growth temperature, and a reduction in CBC with buried SiO2 wires was confirmed. The estimated CBC of the BG-HBT was 7.6 fF, while that of the conventional HBT was 8.6 fF. This 12% reduction was in agreement with the 10% reduction calculated according to the designed size.

Fabrication process for narrow emitter along 010 direction in heterojunction bipolar transistor fully drawn by electron beam lithography was studied. Emitter structure of a 100 nm width was formed by using epitaxial structure with 30-nm-thick InP layer of emitter. Transistor operation of devices with 0.5-µ m-wide emitter was confirmed. This process can be applied to a buried metal heterojunction bipolar transistor (BM-HBT) with narrow emitter, resulting in high-speed operation of BM-HBT.

Lasing action in GaInAs/GaInAsP quantum-wire structure, fabricated by two-step OMVPE growth, electron beam lithography, and wet chemical etching techniques, was obtained for the first time at 77 K with pulsed current injection. GaInAs quantum-wires with size of 10 nm thick and about 30 nm wide were completely separated and embedded in GaInAsP optical confinement layers so as to form a separate-confinement-heterostructure quantum-wire (SCH-QW) laser. The evidence of quantum-wire levels was confirmed by comparing its emission spectrum with that of quantum-film (QF) structure both experimentally and theoretically. The results indicate that there is no serious defects or damages in the laser operation of quantum-wires fabricated by the combination of electron beam lithography, wet chemical etching, and regrowth techniques.

The performance of devices based on two dimensional (2D) materials is significantly affected upon prolonged exposure to atmosphere. We analyzed time based environmental degradation of electrical properties of HfS2 field effect transistors. Atmospheric entities like oxygen and moisture adversely affect the device surface and reduction in drain current is observed over period of 48 hours. Two corrective measures, namely, PMMA passivation and vacuum annealing, have been studied to address the diminution of current by contaminants. PMMA passivation prevents the device from environment and reduces the effect of Coulomb scattering. Improvement in current characteristics signifies the importance of dielectric passivation for 2D materials. On the other hand, vacuum annealing is useful in removing contaminants from the affected surface. In order to figure out optimum process conditions, properties have been studied at various annealing temperatures. The improvement in drain current level was observed upon vacuum annealing within optimum range of annealing temperature.

Mass transport was first employed in an OMVPE system for 1.55 µm GaInAsP/InP laser. The wafers grown by OMVPE were treated at 700 under cracked PH3 and H2+N2 atmosphere for 1 hr, resulting in buried structure and the BH laser showed low threshold current of 50 mA (pulsed) without optimization.

The delay time component (τs) of an InGaAs MOSFET caused by dynamic source resistance is discussed. On the basis of the relationship between the current density (J) and the dynamic source resistance (rs), the value of rs is proportional to 1/J with some offset at low current densities, whereas the offset becomes smaller in a region of high current density. The value of τs depends on the current in a way similar to rs. Because the offset in the high-current-density region is proportional to the square root of the effective mass, an InGaAs MOSFET with a small mass has a shorter rs than a Si MOSFET.

Fabrication of 1.5 µm GaInAsP/InP laser by OMVPE on p-type substrate is reported. Low threshold current density (1.2 kA/cm2) was obtained by reduction of growth time in order to prevent Zn diffusion from substrate. CW operations at room temperature were obtained in buried heterostructure (BH) devices fabricated by OMVPE-LPE hybrid growth method. No degradation was observed after 2000 hours' aging test.

We experimentally demonstrate transistor operation in a vertical p+-MoS2/n-HfS2 van der Waals (vdW) heterostructure configuration for the first time. The HfS2/MoS2 heterojunction transistor exhibits an ON/OFF ratio of 104 and a maximum drain current of 20 nA. These values are comparable with the corresponding reported values for vdW heterojunction TFETs. Moreover, we study the effect of atmospheric exposure on the subthreshold slope (SS) of the HfS2/MoS2 transistor. Unpassivated and passivated devices are compared in terms of their SS values and IDS-VGS hysteresis. While the unpassivated HfS2/MoS2 heterojunction transistor exhibits a minimum SS value of 2000 mV/dec, the same device passivated with a 20-nm-thick HfO2 film exhibits a significantly lower SS value of 700 mV/dec. HfO2 passivation protects the device from contamination caused by atmospheric moisture and oxygen and also reduces the effect of surface traps. We believe that our findings will contribute to the practical realization of HfS2-based vdW heterojunction TFETs.

Current-voltage characteristics of triple-barrier resonant tunneling diodes are theoretically analyzed taking phase breaking into account. The peak current in predicted using conventional theories is much smaller, typically by a factor of 1/3000 for a coherent length of 100 nm, than that measured because the incoherent tunneling process is neglected. We take both the coherent and the incoherent tunneling processes into account in the analysis and show that the product of the peak current and the voltage width at half maximum of the peak current is almost constant even when the phase coherent length varies between 50 and 1000 nm. The peak current density increases by two orders of magnitude in the model developed here.