One of the approaches to improve program understanding is to extract what kinds of design pattern are used in existing object-oriented software. This paper proposes a technique for efficiently and accurately detecting occurrences of design patterns included in source codes. We use both static and dynamic analyses to achieve the detection with high accuracy. Moreover, to reduce computation and maintenance costs, detection conditions are hierarchically specified based on Pree's meta patterns as common structures of design patterns. The usage of Prolog to represent the detection conditions enables us to easily add and modify them. Finally, we have implemented an automated tool as an Eclipse plug-in and conducted experiments with Java programs. The experimental results show the effectiveness of our approach.

For achieving low cross-polarization component in addition to circular-coverage pattern in compact structure, this paper proposes a novel multimode horn with arbitrary coaxial-corrugation configuration which plays two roles of mode converters and chokes. The proposed horn can be designed by iteration of non-linear optimization procedure based on generalized scattering matrices pre-calculated by the mode-matching technique. We show a compact horn with four coaxial corrugations for shaping circular-coverage beam over frequency range of bandwidth 20%. The effectiveness of the designed horn is discussed by evaluating VSWR and radiation characteristics in X-band numerically and experimentally.

Behaviors of an object-oriented system can be visualized as reverse-engineered sequence diagrams from execution traces. This approach is a valuable tool for program comprehension tasks. However, owing to the massiveness of information contained in an execution trace, a reverse-engineered sequence diagram is often afflicted by a scalability issue. To address this issue, many trace summarization techniques have been proposed. Most of the previous techniques focused on reducing the vertical size of the diagram. To cope with the scalability issue, decreasing the horizontal size of the diagram is also very important. Nonetheless, few studies have addressed this point; thus, there is a lot of needs for further development of horizontal summarization techniques. We present in this paper a method for identifying core objects for trace summarization by analyzing reference relations and dynamic properties. Visualizing only interactions related to core objects, we can obtain a horizontally compactified reverse-engineered sequence diagram that contains system's key behaviors. To identify core objects, first, we detect and eliminate temporary objects that are trivial for a system by analyzing reference relations and lifetimes of objects. Then, estimating the importance of each non-trivial object based on their dynamic properties, we identify highly important ones (i.e., core objects). We implemented our technique in our tool and evaluated it by using traces from various open-source software systems. The results showed that our technique was much more effective in terms of the horizontal reduction of a reverse-engineered sequence diagram, compared with the state-of-the-art trace summarization technique. The horizontal compression ratio of our technique was 134.6 on average, whereas that of the state-of-the-art technique was 11.5. The runtime overhead imposed by our technique was 167.6% on average. This overhead is relatively small compared with recent scalable dynamic analysis techniques, which shows the practicality of our technique. Overall, our technique can achieve a significant reduction of the horizontal size of a reverse-engineered sequence diagram with a small overhead and is expected to be a valuable tool for program comprehension.

This paper reviews process, device and circuit technologies of high-density flash memories, whose market has grown explosively as bridge media. In this memory, programming throughput as well as low bit costs is critical issue. To meet the requirements, we have developed multi-level AG (Assist Gate)-AND type flash memory with small effective cell size and 10 MB/s programming throughput. We clarify three challenges to the multilevel flash memory in terms of operation method, high reliability for data retention, and high-speed multilevel programming. Future trends of high-density flash memories are also discussed.

Solution-based organic field-effect transistors (OFETs) with low parasitic capacitance have been fabricated using a self-aligned method. The self-aligned processes using a cross-linking polymer gate insulator allow fabricating electrically stable polymer OFETs with small overlap area between the source-drain electrodes and the gate electrode, whose frequency characteristics have been investigated by impedance spectroscopy (IS). The IS of polymer OFETs with self-aligned electrodes reveals frequency-dependent channel formation process and the frequency response in FET structure.

Framework technology is one of the promising approaches to reuse effectively software and its key issues are 1) to select the suitable frameworks for the software requirements specification, and 2) to fill the suitable hot spots with application-specific codes (customization). This paper proposes a new technique for automated support of the above issues by using labeled transition systems (LTSs) together with metrics technique. We model the behavior of the frameworks and the system behavior specified in the requirements specification by using two LTSs respectively. By establishing bisimilar relationship between the two LTSs, we check whether the behavior of the framework can match to the requirements and explore how to fill its hot spots. This process is done by means of constructing a graph to extract the bisimilar relationships, and each path of the graph denotes one of the implementations of the requirements by the framework. We attach some measures to the LTS of the framework, such as the number of the hot spots to be filled and the number of the parameters to be set up when filling the corresponding hot spot. These measures are used to estimate developer's efforts in filling the hot spots for each implementation, i.e. for each path of the graph. The result of estimating the efforts guides the developers to select the implementation, and the structure of the application-specific codes to be filled in can be automatically generated from the selected implementation. Furthermore we discuss case studies in the area of Web application, where Struts and Turbine can be used.

A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 µm2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.

In this paper, we focus on how to correct address mapping violation, in which an attacker rewrites the address mapping table of a victim to perform a Man-in-the-Middle (MITM) attack. We propose a technique for preventing MITM attacks in which a malicious user intercepts and possibly alters the data transmitted between two hosts. MITM attack is hard for legitimate users to notice during their normal communication, because each user believes they are communicating directly. Address mapping violation can occur because of vulnerability of address resolution protocols, Address Resolution Protocol (ARP) in IPv4 and Neighbor Discovery (ND) protocol in IPv6. Accordingly, a good method to prevent MITM attack by address mapping violation is essential for both current and future communications, i.e. wireless networks with roaming users and an interconnected world. Hence, our proposal mainly aims to have high usability in future applications such as embedded devices.

We investigated collector current spreading in InGaAs single heterojunction bipolar transistors (SHBTs) having a collector thickness of 75 nm. SHBTs were fabricated with three different emitter widths -- 200, 400, and 600 nm -- and the highest cutoff frequency that was obtained was 468 GHz. The relationship between the current density at the highest cutoff frequency and the emitter width could not be used to estimate the current spreading because it was independent of the collector-base voltage. However, the relationship between the current density with the increase in the total collector-base capacitance and the emitter width indicates current spreading in the collector. The current spreading was estimated to be approximately 90 nm.

A 1-Gb AG-AND flash memory has been fabricated using 0.13-µm CMOS technology, resulting in a cell area of 0.104 µm2 and a chip area of 95.2 mm2. By applying constant-charge-injection programming and source-line-select programming, a fast page programming time of 600 µs is achieved. The four-bank operation attains a fast programming throughput of 10 MB/s in multilevel flash memories. The compact SRAM write buffers reduce the chip area penalty. A rewrite throughput of 8.3 MB/s is achieved by means of the RAM-write operation during the erase mode.

A combination of slides used in a presentation and a video recording of the circumstances of the presentation are quite useful for many applications, such as e-learning. However, to create new content from these with current authoring tools requires considerable effort for the author and the products have reduced flexibility. In this paper, we propose the preparation of a unifying function without creating new content manually. We also propose a new approach to search unified presentation manuscripts for slides matched with given keywords by considering the features peculiar to the presentation slides. We propose impression indicators to express how well a slide matches the given keywords. We also propose a system for retrieving a sequence of desired presentation slides from archives of the combined slides and video. We named the system Unified Presentation Slide Retrieval by Impression Search Engine or UPRISE. We describe the system configuration of UPRISE and the experimentation undertaken to evaluate the effect of the proposed indicators and to compare the results with those of the traditional tf.idf retrieval method.

In many parallel processing systems, interference among jobs, which comes from resource contention, causes performance degradation. In order to solve the problem of resource contention, an important question is: "How shall we optimize jop scheduling policy?" However, the traditional queuing theory assuming a first-come-first-served policy is not suitable for analyzing scheduling policy. A new method called Stochastic Petri Nets (SPN) is suitable for analyzing scheduling policy, because with it job arrival states, resource assignment states, and job flow due to these states can be modeled. However, the describing powers of places and transitions, elements of SPN, are as weak as Assembler in program languages. If we model scheduling logic in detail with SPN, that model becomes huge with a great number of places and transitions. Not only modeling of scheduling logic itself becomes difficult, but also analyzing of the model becomes difficult. In this paper, we consider a system in which resource contention causes job interference, and propose a method of analyzing scheduling policy for interference avoidance. In this method, for each scheduling policy, we introduce functions between job execution performance and system states. By incorporating this function into a SPN model, we cut down the size of the model. We apply the proposed method to analyzing performance of the control policy of a magnetic tape library, and show the efficiency and limit of this method.

We developed a selective-capacitance constant-charge-injection programming (CCIP) scheme to achieve high programming throughput in multilevel assist-gate (AG)-AND flash memories. In the conventional CCIP scheme, only one type of capacitance for storing programming charge was used for all levels of multilevel cells. The proposed scheme utilized multiple types of capacitance to minimize the programming time of all levels by using optimized capacitance values for each Vth level. In 4-Gbit AG-AND flash memories, a local bit line capacitance is utilized for mid-level programming, and the sum of local and global bit line capacitance is utilized for top-level programming. In addition, we developed a verify-less programming scheme which reduces top-level programming time because it is not necessary to verify the top-level of multilevel cells in AND flash memory architecture. A programming throughput of 10 MB/s is achieved using the proposed schemes. This is 1.6 times faster than the throughput with conventional CCIP.

One of the critical issue in framework-based software development is a huge introduction cost caused by technical gap between developers and users of frameworks. This paper proposes a technique for deriving framework usages to implement a given requirements specification. By using the derived usages, the users can use the frameworks without understanding the framework in detail. Requirements specifications which describe definite behavioral requirements cannot be related to frameworks in as-is since the frameworks do not have definite control structure so that the users can customize them to suit given requirements specifications. To cope with this issue, a new technique based on satisfiability problems (SAT) is employed to derive the control structures of the framework model. In the proposed technique, requirements specifications and frameworks are modeled based on Labeled Transition Systems (LTSs) with branch conditions represented by predicates. Truth assignments of the branch conditions in the framework models are not given initially for representing the customizable control structure. The derivation of truth assignments of the branch conditions is regarded as the SAT by assuming relations between termination states of the requirements specification model and ones of the framework model. This derivation technique is incorporated into a technique we have proposed previously for relating actions of requirements specifications to ones of frameworks. Furthermore, this paper discuss a case study of typical use cases in e-commerce systems.

Refactoring is one of the promising techniques for improving software design by means of behavior-preserving structural transformation, and is widely taken into practice. In particular, it is frequently applied to design models represented with UML such as class diagrams. However, since UML design models includes multiple diagrams which are closely related from various views, to get behavior-preserving property, we should get the other types of design information and should handle with the propagation of the change on a diagram to the other diagrams. For example, to refactor a class diagram, we need behavioral information of methods included in the class and should also refactor diagrams which represent the behavior, such as state diagrams, activity diagrams. In this paper, we introduce refactoring on design models as transformations of a graph described by UML class diagram and action semantics. First, we define basic transformations of design models that preserve the behavior of designed software, and compose them into refactoring operations. We use Object Constraint Language (OCL) to specify when we can apply a refactoring operation. Furthermore we implement our technique on a graph transformation system AGG to support the automation of refactoring, together with evaluation mechanism of OCL expressions. Some illustrations are presented to show its effectiveness. The work is the first step to handle with refactoring on UML design models in integrated way.

This paper discusses crystal-growth and device-design issues associated with the development of high-performance InP/InGaAs heretostructure bipolar transistors (HBTs). It is shown that a highly Si-doped n+-subcollector in the HBT structure causes anomalous Zn redistribution during metalorganic vapor phase epitaxial (MOVPE) growth. A thermodynamical model of and a useful solution to this big problem are presented. A novel hybrid structure consisting of an abrupt emitter-base heterojunction and a compositionally-graded base is shown to enhance nonequilibrium base transport and thereby increase current gain and cutoff frequency fT. A double-heterostructure bipolar transistor (DHBT) with a step-graded InGaAsP collector can improve collector breakdown behavior without any speed penalty. We also elucidate the effect of emitter size shrinkage on high-frequency performance. Maximum oscillation frequency fmax in excess of 250 GHz is reported.

Self-aligned InP/InGaAs heterojunction bipolar transistors (HBTs) were fabricated with emitter electrodes of 12, 22, 25, and 220 µm2 on the same wafer to investigate the influence of lateral scaling on device performance. DC characterization of these devices showed that InP/InGaAs HBTs are less subject to the emitter-size effect than GaAs-based HBTs. Common-emitter current gain β of the smallest 12-µm2 transistor was approximately 60 which is high enough for practical use. High-frequency characteristics of the transistors were almost the same in spite of the large difference in device size. Unity current-gain cutoff frequency fT of the smallest 12-µm2 transistor was as high as 163 GHz at a collector current of 2.3 mA, which ranks with the fT176 GHz achieved by the largest 220-µm2 transistor at a collector current of 45 mA. The smallest device also showed an excellent high-speed performance of fT100 GHz at submilliampere collector currents of Ic0.6 mA. The results indicate that small-lateral-dimension InP/InGaAs HBTs are applicable to high-speed ICs with low power dissipation.

Program comprehension using dynamic information is one of key tasks of software maintenance. Software visualization with sequence diagrams is a promising technique to help developer comprehend the behavior of object-oriented systems effectively. There are many tools that can support automatic generation of a sequence diagram from execution traces. However it is still difficult to understand the behavior because the size of automatically generated sequence diagrams from the massive amounts of execution traces tends to be beyond developer's capacity. In this paper, we propose an execution trace slicing and visualization method. Our proposed method is capable of slice calculation based on a behavior model which can treat dependencies based on static and dynamic analysis and supports for various programs including exceptions and multi-threading. We also introduce our tool that perform our proposed slice calculation on the Eclipse platform. We show the applicability of our proposed method by applying the tool to two Java programs as case studies. As a result, we confirm effectiveness of our proposed method for understanding the behavior of object-oriented systems.

In this paper, we report the fabrication and device characteristics of InP/InGaAs double heterojunction bipolar transistors (DHBTs) with buried SiO2 wires. The SiO2 wires were buried in the collector and subcollector layers by metalorganic chemical vapor deposition toward reduction of the base-collector capacitance under the base electrode. A current gain of 22 was obtained at an emitter current density of 1.25 MA/cm2 for a DHBT with an emitter width of 400 nm. The DC characteristics of DHBTs with buried SiO2 wires were the same as those of DHBTs without buried SiO2 wires on the same substrate. A current gain cutoff frequency (fT) of 213 GHz and a maximum oscillation frequency (fmax) of 100 GHz were obtained at an emitter current density of 725 kA/cm2.