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Katsutaka KIMURA Toshihiro TANAKA Masataka KATO Tetsuo ADACHI Keisuke OGURA Hitoshi KUME
Programming and program-verification methods for low-voltage flash memories using the Fowler-Nordheim tunneling mechanism for both programming and erasure are described. In these memories, a great many memory cells on a selected word line, such as 512-bytes worth of cells, are programmed at the same time for high-speed programming. The bit-by-bit programming/verification method can precisely control threshold-voltage deviation of programmed memory cells on the selected word line for low voltage operation. By using an internal program-end detection circuit, the completion of program mode can be checked for in one clock cycle, without reading out 512-bytes of data from the memory chip to the external controller. Moreover, the variable pulse-width programming method reduces the total number of verifications.
Hideaki KURATA Satoshi NODA Yoshitaka SASAGO Kazuo OTSUGA Tsuyoshi ARIGANE Tetsufumi KAWAMURA Takashi KOBAYASHI Hitoshi KUME Kazuki HOMMA Teruhiko ITO Yoshinori SAKAMOTO Masahiro SHIMIZU Yoshinori IKEDA Osamu TSUCHIYA Kazunori FURUSAWA
A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 µm2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.
Keiichi HARAGUCHI Hitoshi KUME Masahiro USHIYAMA Makoto OHKURA
A new simple method for extracting the capacitance coupling coefficients of sub-0.5-µm flash memory cells is proposed. Different from the previously proposed methods, this method is not affected by a dopant profile of source region because a band-to-band tunneling current from the interface between the drain and the substrate is probed. Use of a reference device eliminates the necessity to make assumptions concerning the electron transport mechanism. Comparison with the other methods shows that the proposed method is simple and accurate.