A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 µm2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.

We developed a selective-capacitance constant-charge-injection programming (CCIP) scheme to achieve high programming throughput in multilevel assist-gate (AG)-AND flash memories. In the conventional CCIP scheme, only one type of capacitance for storing programming charge was used for all levels of multilevel cells. The proposed scheme utilized multiple types of capacitance to minimize the programming time of all levels by using optimized capacitance values for each Vth level. In 4-Gbit AG-AND flash memories, a local bit line capacitance is utilized for mid-level programming, and the sum of local and global bit line capacitance is utilized for top-level programming. In addition, we developed a verify-less programming scheme which reduces top-level programming time because it is not necessary to verify the top-level of multilevel cells in AND flash memory architecture. A programming throughput of 10 MB/s is achieved using the proposed schemes. This is 1.6 times faster than the throughput with conventional CCIP.