IEICE TRANSACTIONS on Electronics
A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology
Summary :
A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 µm2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.11 pp.2146-2156
- Publication Date
- 2007/11/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.11.2146
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Hideaki KURATA
Satoshi NODA
Yoshitaka SASAGO
Kazuo OTSUGA
Tsuyoshi ARIGANE
Tetsufumi KAWAMURA
Takashi KOBAYASHI
Hitoshi KUME
Kazuki HOMMA
Teruhiko ITO
Yoshinori SAKAMOTO
Masahiro SHIMIZU
Yoshinori IKEDA
Osamu TSUCHIYA
Kazunori FURUSAWA
Keyword
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Hideaki KURATA, Satoshi NODA, Yoshitaka SASAGO, Kazuo OTSUGA, Tsuyoshi ARIGANE, Tetsufumi KAWAMURA, Takashi KOBAYASHI, Hitoshi KUME, Kazuki HOMMA, Teruhiko ITO, Yoshinori SAKAMOTO, Masahiro SHIMIZU, Yoshinori IKEDA, Osamu TSUCHIYA, Kazunori FURUSAWA, "A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 11, pp. 2146-2156, November 2007, doi: 10.1093/ietele/e90-c.11.2146.
Abstract: A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 µm2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.11.2146/_p
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@ARTICLE{e90-c_11_2146,
author={Hideaki KURATA, Satoshi NODA, Yoshitaka SASAGO, Kazuo OTSUGA, Tsuyoshi ARIGANE, Tetsufumi KAWAMURA, Takashi KOBAYASHI, Hitoshi KUME, Kazuki HOMMA, Teruhiko ITO, Yoshinori SAKAMOTO, Masahiro SHIMIZU, Yoshinori IKEDA, Osamu TSUCHIYA, Kazunori FURUSAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology},
year={2007},
volume={E90-C},
number={11},
pages={2146-2156},
abstract={A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 µm2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.},
keywords={},
doi={10.1093/ietele/e90-c.11.2146},
ISSN={1745-1353},
month={November},}
Copy
TY - JOUR
TI - A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 2146
EP - 2156
AU - Hideaki KURATA
AU - Satoshi NODA
AU - Yoshitaka SASAGO
AU - Kazuo OTSUGA
AU - Tsuyoshi ARIGANE
AU - Tetsufumi KAWAMURA
AU - Takashi KOBAYASHI
AU - Hitoshi KUME
AU - Kazuki HOMMA
AU - Teruhiko ITO
AU - Yoshinori SAKAMOTO
AU - Masahiro SHIMIZU
AU - Yoshinori IKEDA
AU - Osamu TSUCHIYA
AU - Kazunori FURUSAWA
PY - 2007
DO - 10.1093/ietele/e90-c.11.2146
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2007
AB - A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 µm2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.
ER -
English
