The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.

Negative differential conductance based on lateral interband tunnel effect is demonstrated in a planar degenerate p+-n+ diode (Esaki tunnel diode). The device is fabricated with the current silicon ultralarge scale integration (Si ULSI) process, paying attention to the processing damage so as to reduce an excess tunnel current that flows over some intermediate states in the tunnel junction. I-V characteristics at a low temperature clearly show an intrinsic electron transport, indicating phonon-assisted tunneling in Si as in the case of the previous Esaki diodes fabricated by the alloying method. In addition, a simple circuit function of bistable operation is demonstrated by connecting the planar Esaki diode with conventional Si metal-oxide-semiconductor field effect transistors (MOSFETs). The planar Esaki diode will be a promising device element in the functional library for enhancing the total system performance for the coming system-on-a-chip (SoC) era.

The edge of a thin SOI (silicon on insulator) film was used to form a very narrow Si-MOS inversion layer. The ultra-thin SOI film was formed by local oxidation of SIMOX wafer. The thickness of the SOI film is less than 15 nm, i.e., the channel width is narrower than 15 nm. At low tempera-tures, clear and large conductance oscillations were seen in this edge channel MOSFET. These oscillations are explained by Coulomb blockade effects in the narrow channel with several effective potential barriers, since the SOI film is so thin that the channel current is seriously affected by small potential fluctuations in the channel. These results suggest that the channel current in edge quantum wire MOSFET can be cut off even with a small controlled potential change. Furthermore, we fabricated a double-gate edge channel Si-MOSFET. In this device, the channel current can be controlled in two ways. One way is to control the electron number inside the isolated electrodes. The other way is to control the threshold voltage of MOSFET. This device enables us to control the phase of Coulomb oscillation.