IEICE TRANSACTIONS on Electronics
Power Consumption of Hybrid Circuits of Single-Electron Transistors and Complementary Metal-Oxide-Semiconductor Field-Effect Transistors
Summary :
The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E84-C No.8 pp.1066-1070
- Publication Date
- 2001/08/01
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Issue on Silicon Nanodevices)
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Ken UCHIDA, Junji KOGA, Ryuji OHBA, Akira TORIUMI, "Power Consumption of Hybrid Circuits of Single-Electron Transistors and Complementary Metal-Oxide-Semiconductor Field-Effect Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1066-1070, August 2001, doi: .
Abstract: The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1066/_p
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@ARTICLE{e84-c_8_1066,
author={Ken UCHIDA, Junji KOGA, Ryuji OHBA, Akira TORIUMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Power Consumption of Hybrid Circuits of Single-Electron Transistors and Complementary Metal-Oxide-Semiconductor Field-Effect Transistors},
year={2001},
volume={E84-C},
number={8},
pages={1066-1070},
abstract={The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Power Consumption of Hybrid Circuits of Single-Electron Transistors and Complementary Metal-Oxide-Semiconductor Field-Effect Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 1066
EP - 1070
AU - Ken UCHIDA
AU - Junji KOGA
AU - Ryuji OHBA
AU - Akira TORIUMI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.
ER -
English
