The search functionality is under construction.
The search functionality is under construction.

Power Consumption of Hybrid Circuits of Single-Electron Transistors and Complementary Metal-Oxide-Semiconductor Field-Effect Transistors

Ken UCHIDA, Junji KOGA, Ryuji OHBA, Akira TORIUMI

  • Full Text Views

    0

  • Cite this

Summary :

The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.

Publication
IEICE TRANSACTIONS on Electronics Vol.E84-C No.8 pp.1066-1070
Publication Date
2001/08/01
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Issue on Silicon Nanodevices)
Category

Authors

Keyword