We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-µm 5-metal CMOS technology.

Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

The current voltage characteristics of the ballistic metal oxide semiconductor field effect transistor (MOSFET) is reviewed. Reducing the carrier scattering by employing e.g. the intrinsic channel structure and the low temperature operation, nanometer to sub-0.1 µm size MOSFETs operation approaches the ballistic transport. The drain current is derived by analyzing the carrier behavior in the vicinity of the potential maximum in the channel. The carrier degeneracy and the predominant carrier distribution in the lowest subband around the maximum point have critical effects on the current value. A convenient approximation of the current in terms of terminal voltages is given. The current control mechanism is discussed with use of the "Injection velocity," with which carriers are injected from the source to the channel. An index to represent the ballisticity is given, and some published experimental data are analyzed. Transport of the quasi-ballistic MOSFET is discussed.

This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.

An effective way to realize scaled CMOS with both requirements of high current drive and low supply voltage is to introduce high mobility channel such as strained Si. This paper proposes a new device structure using the strained-Si channel, strained-Si-on-Insulator (strained-SOI) MOSFET, applicable to sub-100 nm Si CMOS technology nodes. The device structure and the advantages of strained-SOI MOSFETs are presented. It is demonstrated that strained-SOI MOSFETs are successfully fabricated by combining SIMOX technology with re-growth of strained Si and that n- and p-MOSFETs have mobility of 1.6 and 1.3 times higher than the universal one, respectively. Furthermore, it is also shown that ultra-thin SiGe-on-Insulator (SGOI) virtual substrates with higher Ge content, necessary to further increase mobility and to realize fully-depleted SOI MOSFETs, can be made by oxidation of SGOI structure with lower Ge content.

Negative differential conductance based on lateral interband tunnel effect is demonstrated in a planar degenerate p⁺-n⁺ diode (Esaki tunnel diode). The device is fabricated with the current silicon ultralarge scale integration (Si ULSI) process, paying attention to the processing damage so as to reduce an excess tunnel current that flows over some intermediate states in the tunnel junction. I-V characteristics at a low temperature clearly show an intrinsic electron transport, indicating phonon-assisted tunneling in Si as in the case of the previous Esaki diodes fabricated by the alloying method. In addition, a simple circuit function of bistable operation is demonstrated by connecting the planar Esaki diode with conventional Si metal-oxide-semiconductor field effect transistors (MOSFETs). The planar Esaki diode will be a promising device element in the functional library for enhancing the total system performance for the coming system-on-a-chip (SoC) era.

We believe the quantum functional device to be a future perspective device, if we solve the problems that it has nowadays. We will summarize such problems with several discussions from the viewpoint of circuit and system.

Si single-electron transistors with a high voltage gain at a considerably high temperature have been fabricated by vertical pattern-dependent oxidation. The method enables the automatic formation of very small tunnel junctions having capacitances of less than 1 aF. In addition, the use of a thin (a few ten nanometers thick) gate oxide allows a strong coupling of the island to the gate, which results in a gate capacitance larger than the junction capacitances. It is demonstrated at 27 K that an inverting voltage gain, which is governed by the ratio of the gate capacitance to the drain tunnel capacitance, exceeds 3 under constant drain current conditions.

The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.

We analyze electron transport of silicon single-electron transistors (Si SETs) with an ultra-small quantum dot using a master-equation model taking into account the discreteness of quantum levels and the finiteness of scattering rates. In the simulated SET characteristics, aperiodic Coulomb blockade oscillations, fine structures and negative differential conductances due to the quantum mechanical effects are superimposed on the usual Coulomb blockade diagram. These features are consistent with the previously measured results. Large peak-to-valley current ratio of negative differential conductances at room temperature is predicted for Si SETs with an ultra-small dot whose size is smaller than 3 nm.

This paper presents a new multi-target data association method for automotive radar which we call the order statistics joint probabilistic data association (OSJPDA). The method is formulated using the association probabilities of the joint probabilistic data association (JPDA) filter and an optimal target-to-measurement data association is accomplished using the decision logic algorithm. Simulation results for heavily cluttered conditions show that the tracking performance of the OSJPDA filter is better than that of the JPDA filter in terms of tracking accuracy by about 18%.

In this paper, a CMOS down-conversion double-balanced mixer is presented with the modified low voltage design technique. The frequencies of the radio frequency (RF) signal, local oscillator (LO) and intermediate frequency (IF) are 2.4 GHz, 2.3 GHz and 100 MHz, respectively. Measurement results of the proposed mixer exhibit 6.7 dB of conversion gain, -18 dBm of input 1 dB compression point (P_{-1 dB}), -8 dBm of input-referred third-order intercept point (IIP₃), and 14.7 dB single-side band (SSB) noise figure (NF) while applying -8 dBm LO power and consumes 3.3 mA from 1.8 V supply voltage. It can provide 0.7 dB conversion gain when the supply voltage reduces to 1.3 V. This mixer was fabricated in a 0.35 µm 1P4M standard digital CMOS process and the die size is 1.5 1.1 mm².

This paper proposes resolution enhancement techniques for high-speed multi-stage pipelined analog-to-digital converters (ADC's) based on a multi-bit/stage multiplying digital-to-analog converter. The proposed techniques increase ADC resolution and simultaneously minimize chip area, power dissipation, and circuit complexity by removing the gain-proration procedure, which is required in conventional digitally calibrated multi-stage ADC's to reduce unavoidable gain errors between stages with more than two stages calibrated. The resolution of the proposed ADC can be extended furthermore by combining a conventional commutated feedback-capacitor switching scheme with the digital-domain self calibration.

This paper describes a switched-capacitor type DC-DC up converter with high efficiency and low-ripple voltage. Identical charge pumps operating sequentially in the proposed DC-DC converter reduce the magnitude of the ripple voltage to 20% of the conventional converters. A new charge pump adopting PMOS switches near the output stage improves the power efficiency of the DC-DC converter by 10%. The proposed DC-DC converter is applied, as a test vehicle, to a phase-locked loop circuit which is sensitive to power supply noise. All circuits are fabricated and measured in a 0.65-µm CMOS process.

The linearity of the GaAs Field Effect Transistor (FET) power amplifier is greatly influenced by the nonlinear characteristics of gate-source capacitance (C_gs) and drain-source current (I_ds) for the FETs. However, previously suggested analysis methods of GaAs FET non-linearity are mainly focused on the investigations by each individual non-linear component (C_gs or I_ds) without considering both non-linear effects. We analyze more accurately the non-linearity of GaAs FETs by considering non-linear effects of C_gs and I_ds simultaneously. We also investigate the third-order intermodulation distortion (IMD₃) of the GaAs FET in relation to source and load impedances that minimize FET non-linearities. From the simulation results by Volterra-series technique, we show that the least IMD₃ is found at the minimum source resistance (R_S) and maximum load resistance (R_L) in the equivalent output power (P_out) contour. Simulated results are compared with the load and source pull data, with good agreement.

As a method of analyzing the wave scattering from a finite periodic surface, this paper introduces a periodic approach. The approach first considers the wave diffraction by a periodic surface that is a superposition of surface profiles generated by displacing the finite periodic surface by every integer multiple of the period . It is pointed out that the Floquet solution for such a periodic case becomes an integral representation of the scattered field from the finite periodic surface when the period goes to infinity. A mathematical relation estimating the scattering amplitude for the finite periodic surface from the diffraction amplitude for the periodic surface is proposed. From some numerical examples, it is concluded that the scattering cross section for the finite periodic surface can be well estimated from the diffraction amplitude for a sufficiently large .