IEICE TRANSACTIONS on Electronics
An Area-Effective Datapath Architecture for Embedded Microprocessors and Scalable Systems
Summary :
We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-µm 5-metal CMOS technology.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E84-C No.8 pp.1014-1020
- Publication Date
- 2001/08/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on Silicon Nanodevices)
- Category
Authors
Toshiaki INOUE
Takashi MANABE
Sunao TORII
Satoshi MATSUSHITA
Masato EDAHIRO
Naoki NISHI
Masakazu YAMASHINA
Keyword
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Toshiaki INOUE, Takashi MANABE, Sunao TORII, Satoshi MATSUSHITA, Masato EDAHIRO, Naoki NISHI, Masakazu YAMASHINA, "An Area-Effective Datapath Architecture for Embedded Microprocessors and Scalable Systems" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1014-1020, August 2001, doi: .
Abstract: We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-µm 5-metal CMOS technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1014/_p
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@ARTICLE{e84-c_8_1014,
author={Toshiaki INOUE, Takashi MANABE, Sunao TORII, Satoshi MATSUSHITA, Masato EDAHIRO, Naoki NISHI, Masakazu YAMASHINA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Area-Effective Datapath Architecture for Embedded Microprocessors and Scalable Systems},
year={2001},
volume={E84-C},
number={8},
pages={1014-1020},
abstract={We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-µm 5-metal CMOS technology.},
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - An Area-Effective Datapath Architecture for Embedded Microprocessors and Scalable Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 1014
EP - 1020
AU - Toshiaki INOUE
AU - Takashi MANABE
AU - Sunao TORII
AU - Satoshi MATSUSHITA
AU - Masato EDAHIRO
AU - Naoki NISHI
AU - Masakazu YAMASHINA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-µm 5-metal CMOS technology.
ER -
English
