We have proposed the high-density triangular parallel wire channel MOSFET on an SOI substrate and demonstrated the suppressed short channel effects by simulation and experiment. In this device structure, the fabrication process is fully compatible with the planar MOSFET process and is much less complicated than other non-planer device structures including gate-all-around (GAA) and double-gate SOI MOSFETs. In addition, our fabrication process makes it possible to double the wire density resulting in the higher current drive. The three-dimensional simulation results show that the proposed triangular wire channel MOSFET has better short channel characteristics than single-gate and double-gate SOI MOSFETs. The fabricated triangular parallel wire channel MOSFETs show better subthreshold characteristics and less drain induced barrier lowering (DIBL) than the single-gate SOI MOSFETs.

An 18-kb RAM with 9-kgate control logic gates operating during a cycle-time of 1.5 ns has been developed. A pseudo-dual-port RAM function is achieved by a two-bank structure and on-chip control logic. Each bank can operate individually with different address synchronizing the single clock. A sense-amplifier with a selector function reduces the reading propagation time. Bonded SOI wafers reduce the memory-cell capacitance, and this results in a fast write cycle without sacrificing α-particle immunity. The chip is fabricated in a double polysilicon self-aligned bipolar process using trench isolation. The minimum emitter size is 0.52 µm2 and the chip size is 1111 mm2.

The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, variable-body-factor FD SOI MOSFET and multigate MOSFET with low aspect ratio, have been proposed and their advantages are discussed.

We analyze electron transport of silicon single-electron transistors (Si SETs) with an ultra-small quantum dot using a master-equation model taking into account the discreteness of quantum levels and the finiteness of scattering rates. In the simulated SET characteristics, aperiodic Coulomb blockade oscillations, fine structures and negative differential conductances due to the quantum mechanical effects are superimposed on the usual Coulomb blockade diagram. These features are consistent with the previously measured results. Large peak-to-valley current ratio of negative differential conductances at room temperature is predicted for Si SETs with an ultra-small dot whose size is smaller than 3 nm.

A new BiCMOS process based on a high-speed bipolar process with 0.5 µm emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.

Distribution of current onset voltage (COV) as well as threshold voltage (VTH) and drain induced barrier lowering (DIBL) in MOSFETs fabricated by 65 nm technology is statistically analyzed. Although VTH distribution follows the normal distribution, COV and DIBL deviate from the normal distribution. It is newly found that COV follows the Gumbel distribution, which is known as one of the extreme value distributions. This result of statistical COV analysis supports our model that COV is mainly determined by the deepest potential valley between source and drain.

We have studied the characteristic trade-offs in low power and low voltage MOSFETs from the viewpoint of back-gate control and body effect factor. Previously reported MOSFET structures are classified into four categories in terms of back-gate structures. It is shown that a MOSFET with a fixed back-bias has only a limited current drive at low voltage irrespective of device structures, while current drive of a dynamic threshold MOSFET with body tied to gate is more enhanced with increasing body effect factor. We have proposed a new dynamic threshold MOSFET, electrically induced body (EIB) DTMOS, which has a very large body effect factor at low threshold voltage and high current drive at low supply voltage.

The self-improvement of static random access memory (SRAM) cell stability by post-fabrication high-voltage stress is experimentally demonstrated and its mechanism is analyzed using 4k device-matrix-array (DMA) SRAM test element group (TEG). It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to the VDD terminal of SRAM. It is newly found that | VTH| of the OFF-state pFETs in the SRAM cell is selectively lowered which improves the cell stability and contributes to the self-improvement.

In this paper, negative bias temperature instability (NBTI) reliability of pFETs is analyzed under the post-fabrication SRAM self-improvement scheme that we have developed recently, where cell stability is self-improved by simply applying high stress voltage to supply voltage terminal (VDD) of SRAM cells. It is newly found that there is no significant difference in both threshold voltage and drain current degradation by NBTI stress between fresh PFETs and PFETs after self-improvement scheme application, indicating that the self-improvement scheme has no critical reliability problem.