IEICE TRANSACTIONS on Electronics
Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations
Summary :
The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, variable-body-factor FD SOI MOSFET and multigate MOSFET with low aspect ratio, have been proposed and their advantages are discussed.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.836-841
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.4.836
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
- Category
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Toshiro HIRAMOTO, Toshiharu NAGUMO, Tetsu OHTOU, Kouki YOKOYAMA, "Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 4, pp. 836-841, April 2007, doi: 10.1093/ietele/e90-c.4.836.
Abstract: The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, variable-body-factor FD SOI MOSFET and multigate MOSFET with low aspect ratio, have been proposed and their advantages are discussed.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.836/_p
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@ARTICLE{e90-c_4_836,
author={Toshiro HIRAMOTO, Toshiharu NAGUMO, Tetsu OHTOU, Kouki YOKOYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations},
year={2007},
volume={E90-C},
number={4},
pages={836-841},
abstract={The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, variable-body-factor FD SOI MOSFET and multigate MOSFET with low aspect ratio, have been proposed and their advantages are discussed.},
keywords={},
doi={10.1093/ietele/e90-c.4.836},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations
T2 - IEICE TRANSACTIONS on Electronics
SP - 836
EP - 841
AU - Toshiro HIRAMOTO
AU - Toshiharu NAGUMO
AU - Tetsu OHTOU
AU - Kouki YOKOYAMA
PY - 2007
DO - 10.1093/ietele/e90-c.4.836
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, variable-body-factor FD SOI MOSFET and multigate MOSFET with low aspect ratio, have been proposed and their advantages are discussed.
ER -
English
