In this study, the transient characteristics on the super-steep subthreshold slope (SS) of a PN-body tied (PNBT) silicon-on-insulator field-effect transistor (SOI-FET) were investigated using technology computer-aided design and pulse measurements. Carrier charging effects were observed on the super-steep SS PNBT SOI-FET. It was found that the turn-on delay time decreased to nearly zero when the gate overdrive-voltage was set to 0.1-0.15 V. Additionally, optimizing the gate width improved the turn-on delay. This has positive implications for the low speed problems of this device. However, long-term leakage current flows on turn-off. The carrier lifetime affects the leakage current, and the device parameters must be optimized to realize both a high on/off ratio and high-speed operation.

We report the characterization of hysteresis in SOI-based super-steep subthreshold slope FETs, which are conventional floating body and body-tied, and newly proposed PN-body-tied structures. We found that the hysteresis widths of the PN-body-tied structures are smaller than that of the conventional floating body and body-tied structures; this means that they are feasible for switching devices. Detailed characterizations of the hysteresis widths of each device are also reported in the study, such as dependency on the gate length and the impurity concentration.

This paper proposes a novel approach for implementing an ultra-low-power voltage reference using the structure of self-cascode MOSFET, operating in the subthreshold region with a self-biased body effect. The difference between the two gate-source voltages in the structure enables the voltage reference circuit to produce a low output voltage below the threshold voltage. The circuit is designed with only MOSFETs and fabricated in standard 0.18-µm CMOS technology. Measurements show that the reference voltage is about 107.5 mV, and the temperature coefficient is about 40 ppm/, at a range from -20 to 80. The voltage line sensitivity is 0.017%/V. The minimum supply voltage is 0.85 V, and the supply current is approximately 24 nA at 80. The occupied chip area is around 0.028 mm2.

Leakage current for MOSFET in off-state is one of the serious problems in charge-based analog circuits under low power supply. To suppress the leakage current, a method that a slight voltage is applied to source to accomplish reverse bias between source and bulk is proposed. The proposed bias condition, also other bias conditions, is analyzed by injection carrier density in p-n junction and surface carrier concentration in MOS diode in four-terminal MOSFET. Leakage current is modeled by combining the characteristics of p-n junction with MOS diode in MOSFET. The characteristics of MOSFET fabricated with a standard 0.18 µm n-well CMOS technology are measured to investigate the basic principle. Measured leakage current fits to the theoretical leakage current exactly. The proposed slight bias to source terminal in MOSFET is proved most efficient to reduce the leakage current. Based on the proposed source bias condition, MOSFET switches with low leakage current under a single power supply are proposed.

The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, variable-body-factor FD SOI MOSFET and multigate MOSFET with low aspect ratio, have been proposed and their advantages are discussed.

A low-power sub-1-V self-biased low-voltage reference is proposed for micropower electronic applications based on body effect. The proposed reference has a very low temperature dependence by using a MOSFET with body effect compared with other reported low-power references. An HSPICE simulation shows that the reference voltage and the total power dissipation are 181 mV and 1.1 µW, respectively. The temperature coefficient of the reference voltage is 33 ppm/ at temperatures from -40 to 100. The supply voltage can be as low as 0.95 V in a standard CMOS 0.35 µm technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. Furthermore, the supply voltage dependence is -0.36 mV/V (Vdd=0.95-3.3 V).

The port-to-port isolation of the micromixer is studied using three different p-type downconversion micromixers in 0.35-µm CMOS technology. Both the body effect and the well isolation influence the port-to-port isolation significantly. The body effect degrades the LO-to-IF isolation and also deteriorates the LO-to-RF isolation. Without the well isolation, the LO-to-RF isolation drops. However, the RF-to-IF isolation is independent of the body effect and well isolation. The p-type micromixer with a separate N-well and without body effect has the best port-to-port isolation properties; its LO-to-IF, LO-to-RF, and RF-to-IF isolations are -59 dB, -58 dB, and -30 dB, respectively.

The threshold voltage mismatch of FD (Fully depleted) SOI (Silicon on insulator) devices have been studied. Floating body MOSFETs operating at high drain voltage show a large mismatch in the threshold voltage compared with body-tied MOSFETs. Those experimental data under different drain voltages indicate that both floating body effect and DIBL (Drain induced barrier lowering) are involved in the threshold voltage mismatch of floating body MOSFETs.

As the capacity of a personal computer and workstation increases rapidly, many electromagnetic simulators solving antenna problems are widely used. In this paper, the IE3D, FIDELITY and HFSS electromagnetic simulators, which are commercial software products, are applied to the analysis of built-in antennas for handsets in the vicinity of the human body. The IE3D, FIDELITY and HFSS electromagnetic simulators are based on the methods of moment, FDTD (Finite Difference Time Domain) and FEM (Finite Element Method), respectively. Firstly, basic characteristics including the human body's effect of a popular built-in antenna for handset such as PIFA (Planar Inverted-F Antenna) are obtained by the IE3D, FIDELITY and HFSS electromagnetic simulators, and calculated results are compared with measured results. Secondly, on the basis of newly considered design concepts for a handset antenna, a folded loop antenna for handset, which we have proposed in order to reduce the influence of the human body, is taken as an example of a balance-fed antenna and is analyzed theoretically and experimentally including the influence of the human body. In a result, calculated results by these three kinds of electromagnetic simulators are in good agreement with measured results and it is confirmed that these simulators are very effective in analyzing the handset antenna in the vicinity of the human body.

Analysis of a novel folded loop antenna for handset is described along with the advanced design concept for handset antennas. The design concept shown in this paper meets the foremost requirement for handset antennas such as (1) small size and yet (2) has capability of mitigating degradation of antenna performance due to the body effect, and (3) of reducing SAR value in the human head at the handset talk position, in addition to the indispensable requirements for handset antennas such as (4) low profile, and (5) light weight. The technology applied is to make this antenna (a) an integrated structure, which is a typical application of the fundamental concept of making antennas small and (b) a balanced structure which has been proved to be very effective to satisfy the requirements (2) and (3). The antenna is essentially a two-wire transmission line, folded at about a quarter-wavelength to form a half-wave folded dipole, and yet appears to be a loop of one-wavelength. It does not have really a balanced structure, as is fed with an unbalanced line; however, the antenna structure itself can eliminate the unbalanced current flow on the feed line as in the balanced antenna system. Both theoretical and experimental analyses have been shown and the usefulness of the antenna is discussed. This paper may suggest the advanced technology and design concept that will be applied to the development of handset antennas toward the future.

As the capacity of a personal computer and workstation increases rapidly, many electromagnetic simulators solving antenna problems are widely used. In this paper, the IE3D electromagnetic simulator, which is a commercial software product, is applied to the analysis of handset antennas in the vicinity of the human body. Firstly, basic characteristics of popular handset antennas such as whip and planar inverted-F antennas are obtained by the IE3D electromagnetic simulator and calculated results are compared with measured results quoted from the referenced paper. Secondly, on the basis of newly considered design concept for a handset antenna, a loop antenna system for the handset, which we have proposed in order to reduce the influence of human body, is taken as an example of a balance-fed antenna and is analyzed theoretically and experimentally including the influence of the human body. In a result, calculated results by the IE3D electromagnetic simulator are in good agreement with measured results and it is confirmed that the simulator is very effective in analyzing the handset antenna in the vicinity of the human body.

In this paper, we propose an effective SOI yield engineering methodology by practical usage of 2D simulations. Process design for systematic yield of Fully-Depleted SOI MOSFET requires specific consideration of floating-body effects and parasitic channel leakage currents. The influence of varied SOI layer thickness to such phenomena is also complicated and substantial. Instead of time-consuming 3D simulators, 2D simulators are used to optimize the process considering these effects in acceptable turn around time. Our methodology is more effective in future scaled-down process with decreased SOI layer thickness.

We have studied the characteristic trade-offs in low power and low voltage MOSFETs from the viewpoint of back-gate control and body effect factor. Previously reported MOSFET structures are classified into four categories in terms of back-gate structures. It is shown that a MOSFET with a fixed back-bias has only a limited current drive at low voltage irrespective of device structures, while current drive of a dynamic threshold MOSFET with body tied to gate is more enhanced with increasing body effect factor. We have proposed a new dynamic threshold MOSFET, electrically induced body (EIB) DTMOS, which has a very large body effect factor at low threshold voltage and high current drive at low supply voltage.

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.

Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2µm fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a nonuniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.

This paper presents a new piecewise-linear dc model of the MOSFET. The proposed model is derived for long channel MOSFETs from the Shichman-Hodges equations, with emphasis on the accurate modeling of the major electrical characteristics, and is extended for short channel MOSFETs. The performance of the model is evaluated by comparing current-voltage characteristics and voltage transfer characteristics with those of the SPICE level-l and Sakurai models. The experimental results, using three or fewer piecewise-linear region boundaries on the axes of VGS, VGD and VSB, demonstrate that the proposed model provides enough accuracy for practical use with digital circuits.