In this paper, we review a super-steep subthreshold slope (SS) (<1 mV/dec) body-tied (BT) silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) fabricated with 0.15 µm SOI technology and discuss the possibility of its use in ultralow voltage applications. The mechanism of the super-steep SS in the BT SOI MOSFET was investigated with technology computer-aided design simulation. The gate length/width and Si thickness optimizations promise further reductions in operation voltage, as well as improvement of the ION/IOFF ratio. In addition, we demonstrated control of the threshold voltage and hysteresis characteristics using the substrate and body bias in the BT SOI MOSFET.

A CMOS design to achieve high drivability is examined for lower power supply voltage in 0.5 µm ULSI. The design consists of two points. (1) A very narrow (50 nm) sidewall is used to achieve high drivability and also to obtain hot-carrier-reliability. (2) A retrograded channel profile with NMOS and PMOS is designed to achieve high drivability and also to reduce short channel effect. It is shown that the propagation delay times (tpd) of a unloaded Inverter and a loaded 2-way NAND gate are improved 30% with the newly designed CMOS, compared with the conventionally designed CMOS. It is also proved that the tpd keeps the scaling trend of the previous-5 V-era even in 3.3 V-era by adapting the newly designed CMOS. Moreover, 7.1 ns multiplication time of 1616-bit multiplier is obtained under 0.5 µm design rule.

In this study, the transient characteristics on the super-steep subthreshold slope (SS) of a PN-body tied (PNBT) silicon-on-insulator field-effect transistor (SOI-FET) were investigated using technology computer-aided design and pulse measurements. Carrier charging effects were observed on the super-steep SS PNBT SOI-FET. It was found that the turn-on delay time decreased to nearly zero when the gate overdrive-voltage was set to 0.1-0.15 V. Additionally, optimizing the gate width improved the turn-on delay. This has positive implications for the low speed problems of this device. However, long-term leakage current flows on turn-off. The carrier lifetime affects the leakage current, and the device parameters must be optimized to realize both a high on/off ratio and high-speed operation.

The local wiring structure which is known as a technique for reducing junction capacitance due to the area reduction of the Source/Drain junction by the "on-field" contact scheme was constructed. Its effect on speed/power improvement was evaluated with a ring oscillator. A speed improvement of 15% and a 17% reduction in power dissipation was obtained as compared with conventional non-local wiring structures. This technique was applied to a practical device application, that is, a 0.35 µm embedded dual port SRAM used as a buffer memory in an asynchronous transfer mode switch (ATM-SW) LSI. In order to suppress the coupling noise between the write and read bitlines with the small cell realized by the local wiring scheme, a new divided layer 'bitline architecture was developed. As a result, reduction of SRAM macro size of 31% was attained by also applying the local wiring scheme to peripheral circuits, such as decoder, sense amplifier, and driver. A detailed analysis on this embedded dual port SRAM revealed a 15.2% reduction of write port power at 3.3 V. It is also shown that the local wiring technique is more effective with low power supply voltages to allow for further power reduction.

We report the characterization of hysteresis in SOI-based super-steep subthreshold slope FETs, which are conventional floating body and body-tied, and newly proposed PN-body-tied structures. We found that the hysteresis widths of the PN-body-tied structures are smaller than that of the conventional floating body and body-tied structures; this means that they are feasible for switching devices. Detailed characterizations of the hysteresis widths of each device are also reported in the study, such as dependency on the gate length and the impurity concentration.