A new analog correlator circuit is proposed for direct sequence code division multiple access (DS-CDMA) demodulator. The circuit consists of only 16 switches, 4 capacitors and 2 level shifters. Control sequence requires only three clock phases. Simulation with code length of 127 reveals that the proposed circuit has a good ability to cancel off the charge error and dissipates 3.4mW at 128MHz. The circuit had been designed using a 0.6µm CMOS process. The area of 256µm 245µm is estimated to be 9 times smaller compared to other reported equivalent analog correlators.

Hot carrier effects in narrow-channel MOSETs are investigated. With decreasing channel width below 1µm, the ratio of substrate to channel currents show marked increase. By using the newly developed full three-dimensional process/device simulation system, two significant causes of the hot carrier effects are clarified.

Thickness dependence of breakdown properties in control and N2O-Oxynitrided oxides was investigated. Nitrogen atoms piled up at the Si/SiO2 interface increase charge-to-breakdown (QBD) under substrate injection conditions for oxide thickness below 10 nm, while no meaningful improvement is observed above 10 nm. This thickness dependence is explained by the fact that N2O-oxynitridation reduces oxide defects near the Si/SiO2 interface. N2O-oxynitridation of the oxides reduces the number of neutral electron traps due to the chemical reaction of oxide defect with nitrogen atoms. Electron trapping of N2O-oxynitrided oxides is significantly suppressed; the reduction of electron trapping events into neutral electron traps increases QBD under substrate injection. On the other hand, under gate injection, N2O-oxynitrided oxides show low rate of hole trapping during the initial stress period. However, in heavily injected condition, electron trapping is not suppressed, resulting in little improvement of QBD. In addition, the control and N2O-oxynitrided oxides show quite similar dependence of QBD on stress current density, which is related primarily to the carrier transport phenomena (tunneling, traveling, impact ionization and hole injection).

We propose a nonlocal impact ionization model applicable for the drain region where electric field increases exponentially. It is expressed as a function of an electric field and a characteristic length which is determined by a thickness of gate oxide and a source/drain junction depth. An analytical substrate current model for n-MOSFET is also derived from the new nonlocal impact ionization model. The model well explains the reason why the theoretical characteristic length differs from empirical expressions used in a pseudo two-dimensional model for MOSFET's. The nonlocal impact ionization model implemented in a device simulator demonstrates that the new model can predict substrate current correctly in the framework of drift-diffusion model.

We propose an ultra low power watch-dog circuit with the use of MOSFETs operation under subthreshold characteristics. The circuit monitors the amount of the product degradation because the subthreshold current of MOSFET emulates the rate of the general chemical reaction. Its operation was verified with both SPICE simulation and the measurement of the prototype chip. The new circuit embedded in a tag attached to any product could dynamically monitor the degradation regardless of storage conditions.

A dynamic dither gain control technique for multi-level delta-sigma Digital-to-Analog Converters (DACs) using multi-stage Dynamic Element Matching (DEM) with a second order loop filter is proposed. The proposed technique provides improvement on the mismatch shaping performance through dynamic control of delta-sigma modulator dither gain. A large dither gain, which suppresses DEM operation dependency on input signal, is applied to delta-sigma modulator, when DEM loop filter output is greater than a designed reference. The design example using the proposed technique on a third order 17-level delta-sigma modulator with 3-stage cascaded DEM is shown in this paper. Simulation result with 1% analog segment mismatch shows over 10 dB improvement of THD+N performance under -50 dB amplitude input signal, compared to the case without the proposed technique.

A reference voltage buffer for a multibit/stage pipelined ADC is described, where a settling boost technique is used to improve the settling response of the pipelined stages. A 12 bit 18 MHz pipelined ADC with the buffer is designed and simulated based on a 0.35 µm CMOS process. According to simulation results, the power consumed by the reference voltage buffer is reduced by 33% compared to that without the settling boost technique.

This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm 4.5 mm chip using 0.6 µm CMOS process.

The basic operation characteristics of an asymmetric turnstile which transfers each electron one by one in one direction is described. A novel single electron counter circuit consisting of the asymmetric turnstiles, a load capacitor and an inverter which counts the number of high inputs is proposed. Monte Carlo circuit simulations reveal that the gate clock time of the counter circuit should be long enough to achieve allowable minimum error rate. The counter circuit implementing asymmetric single electron turnstiles is demonstrated to be applicable to a noise reduction system, a Winner-Take-All circuit and an artificial neuron circuit.

In the present paper, procedures for extracting nucleoli from leukocyte images are proposed. Main processed procedures consist of the filtering operation in the frequency domain, the edge preserving smoothing, the extraction of the nuclear region, the edge detection and the decision of nucleolar regions. By applying proposed procedures, nucleoli can be extracted easily and precisely from the nucleus if we can clearly see nucleoli with human eyes. We were able to achieve the correct discrimination of 82 percent of nucleoli in immature leukocytes.

Wired CDMA interface with adaptivity for interconnect capacitances is designed to receive transmitted data even under a wide variety of connection topologies. The variable gain amplifier (VGA) is one of key circuit blocks to realize the adaptivity for interconnect capacitances. The system level numerical simulations derive the VGA specifications that the required VGA gain range is from 0.37 to 2.0, which can be realized easily using a multiple-differential-pair technique.

A low power and high performance with third order delta-sigma modulator for audio applications, fabricated in a 0.18 µm CMOS process, is presented. The modulator utilizes a third order noise shaping with only one opamp by using an opamp sharing technique. The opamp sharing among three integrator stages is achieved through the optimal operation timing, which makes use of the load capacitance differences between the three integrator stages. The designed modulator achieves 101.1 dB signal-to-noise ratio (A-weighted) and 101.5 dB dynamic range (A-weighted) with 7.5 mW power consumption from a 3.3 V supply. The die area is 1.27 mm2. The fabricated delta-sigma modulator achieves the highest figure-of-merit among published high performance low power audio delta-sigma modulators.

A signal detection system using noise statistical processing is proposed. By approaching the problems of low voltage and high noise from miniaturization of a device from a stochastic point of view, a faint-signal receiving system that can effectively detect subthreshold and noise level signals has been developed. In addition, an alternative to statistical processing is proposed, and would be successfully implemented on a circuit. For the proposed signal detection method, the detection sensitivity was investigated using numerical simulation, and the detection sensitivity was sufficiently high to detect even a signal with a signal-to-inherent-noise ratio of -14 dB. Thus, it is anticipated that the application of this system to an integrated circuit will have a significant impact on signal processing.

This paper introduces several techniques for achieving RF and analog CMOS circuits for wireless communication systems under ultra-low-voltage supply, such as 0.5 V. Forward body biasing and inverter-based circuit techniques were applied in the design of a feedforward Δ-ΣA/D modulator operating with a 0.5 V supply. Transformer utilization is also presented as an inductor area reduction technique. In addition, application of stochastic resonance to A/D conversion is discussed as a future technology.

This paper presents the design consideration of a four-stage variable gain amplifier (VGA) with a wide dynamic range for receivers. The VGA uses parallel amplifiers for the first and second amplifiers in order to improve the input third-order intercept point (IIP3) in the low gain region. To investigate the behavior of the VGA, the gain and linearity analyses are newly derived for the parallel amplifiers, and are compared with the measured results. In addition, the principle of the temperature compensation is described. The gain control range of 110 dB, the IP1 dB of -11 dBm, and noise figure (NF) of 5.1 dB were measured using a 0.5 µm 26 GHz fT BiCMOS process.

This paper describes the design of a random access memory (RAM) bank with a 0.35-µm CMOS process for column-parallel analog/digital converters (ADC) utilized in CMOS imagers. A dynamic latch is utilized that expends neither input DC nor drain current during the monitoring phase. Accuracy analysis of analog/digital conversion error in the RAM bank is discussed to ensure low power consumption of a counter buffer circuit. Moreover, the counter buffer utilizes a combination of NMOS and CMOS buffers to reduce power consumption. Total power consumption of a 10-bit 800-column 40 MHz RAM bank is 2.9 mA for use in an imager.

For wireless communication, a low-voltage monolithic LC-tank CMOS voltage-controlled-oscillator (VCO) is developed with 0.2-µm fully-depleted silicon-on-insulator (SOI) CMOS process technology. The VCO features a double-tuning technique to achieve a wide tuning range with lateral p-n junction varactors. The VCO has the following features at the supply voltage of 1.5 V: (1) Output frequency range from 1.07 GHz to 1.36 GHz, (2) Third-harmonic below -37 dBc, and (3) Phase noise of -120 dBc/Hz at 1 MHz offset frequency.

The threshold voltage mismatch of FD (Fully depleted) SOI (Silicon on insulator) devices have been studied. Floating body MOSFETs operating at high drain voltage show a large mismatch in the threshold voltage compared with body-tied MOSFETs. Those experimental data under different drain voltages indicate that both floating body effect and DIBL (Drain induced barrier lowering) are involved in the threshold voltage mismatch of floating body MOSFETs.