IEICE TRANSACTIONS on Fundamentals
A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter
Summary :
A reference voltage buffer for a multibit/stage pipelined ADC is described, where a settling boost technique is used to improve the settling response of the pipelined stages. A 12 bit 18 MHz pipelined ADC with the buffer is designed and simulated based on a 0.35 µm CMOS process. According to simulation results, the power consumed by the reference voltage buffer is reduced by 33% compared to that without the settling boost technique.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.2 pp.367-373
- Publication Date
- 2009/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.367
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
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Shunsuke OKURA, Tetsuro OKURA, Toru IDO, Kenji TANIGUCHI, "A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 2, pp. 367-373, February 2009, doi: 10.1587/transfun.E92.A.367.
Abstract: A reference voltage buffer for a multibit/stage pipelined ADC is described, where a settling boost technique is used to improve the settling response of the pipelined stages. A 12 bit 18 MHz pipelined ADC with the buffer is designed and simulated based on a 0.35 µm CMOS process. According to simulation results, the power consumed by the reference voltage buffer is reduced by 33% compared to that without the settling boost technique.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.367/_p
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@ARTICLE{e92-a_2_367,
author={Shunsuke OKURA, Tetsuro OKURA, Toru IDO, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter},
year={2009},
volume={E92-A},
number={2},
pages={367-373},
abstract={A reference voltage buffer for a multibit/stage pipelined ADC is described, where a settling boost technique is used to improve the settling response of the pipelined stages. A 12 bit 18 MHz pipelined ADC with the buffer is designed and simulated based on a 0.35 µm CMOS process. According to simulation results, the power consumed by the reference voltage buffer is reduced by 33% compared to that without the settling boost technique.},
keywords={},
doi={10.1587/transfun.E92.A.367},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 367
EP - 373
AU - Shunsuke OKURA
AU - Tetsuro OKURA
AU - Toru IDO
AU - Kenji TANIGUCHI
PY - 2009
DO - 10.1587/transfun.E92.A.367
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2009
AB - A reference voltage buffer for a multibit/stage pipelined ADC is described, where a settling boost technique is used to improve the settling response of the pipelined stages. A 12 bit 18 MHz pipelined ADC with the buffer is designed and simulated based on a 0.35 µm CMOS process. According to simulation results, the power consumed by the reference voltage buffer is reduced by 33% compared to that without the settling boost technique.
ER -
English
