IEICE TRANSACTIONS on Fundamentals
A New Analog Correlator Circuit for DS-CDMA Wireless Applications
Summary :
A new analog correlator circuit is proposed for direct sequence code division multiple access (DS-CDMA) demodulator. The circuit consists of only 16 switches, 4 capacitors and 2 level shifters. Control sequence requires only three clock phases. Simulation with code length of 127 reveals that the proposed circuit has a good ability to cancel off the charge error and dissipates 3.4mW at 128MHz. The circuit had been designed using a 0.6µm CMOS process. The area of 256µm
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.5 pp.1294-1301
- Publication Date
- 2003/05/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Spread Spectrum Technologies and Applications
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Mostafa A. R. ELTOKHY, Boon-Keat TAN, Toshimasa MATSUOKA, Kenji TANIGUCHI, "A New Analog Correlator Circuit for DS-CDMA Wireless Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 5, pp. 1294-1301, May 2003, doi: .
Abstract: A new analog correlator circuit is proposed for direct sequence code division multiple access (DS-CDMA) demodulator. The circuit consists of only 16 switches, 4 capacitors and 2 level shifters. Control sequence requires only three clock phases. Simulation with code length of 127 reveals that the proposed circuit has a good ability to cancel off the charge error and dissipates 3.4mW at 128MHz. The circuit had been designed using a 0.6µm CMOS process. The area of 256µm
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_5_1294/_p
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@ARTICLE{e86-a_5_1294,
author={Mostafa A. R. ELTOKHY, Boon-Keat TAN, Toshimasa MATSUOKA, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New Analog Correlator Circuit for DS-CDMA Wireless Applications},
year={2003},
volume={E86-A},
number={5},
pages={1294-1301},
abstract={A new analog correlator circuit is proposed for direct sequence code division multiple access (DS-CDMA) demodulator. The circuit consists of only 16 switches, 4 capacitors and 2 level shifters. Control sequence requires only three clock phases. Simulation with code length of 127 reveals that the proposed circuit has a good ability to cancel off the charge error and dissipates 3.4mW at 128MHz. The circuit had been designed using a 0.6µm CMOS process. The area of 256µm
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - A New Analog Correlator Circuit for DS-CDMA Wireless Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1294
EP - 1301
AU - Mostafa A. R. ELTOKHY
AU - Boon-Keat TAN
AU - Toshimasa MATSUOKA
AU - Kenji TANIGUCHI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2003
AB - A new analog correlator circuit is proposed for direct sequence code division multiple access (DS-CDMA) demodulator. The circuit consists of only 16 switches, 4 capacitors and 2 level shifters. Control sequence requires only three clock phases. Simulation with code length of 127 reveals that the proposed circuit has a good ability to cancel off the charge error and dissipates 3.4mW at 128MHz. The circuit had been designed using a 0.6µm CMOS process. The area of 256µm
ER -
English
