We have studied the characteristic trade-offs in low power and low voltage MOSFETs from the viewpoint of back-gate control and body effect factor. Previously reported MOSFET structures are classified into four categories in terms of back-gate structures. It is shown that a MOSFET with a fixed back-bias has only a limited current drive at low voltage irrespective of device structures, while current drive of a dynamic threshold MOSFET with body tied to gate is more enhanced with increasing body effect factor. We have proposed a new dynamic threshold MOSFET, electrically induced body (EIB) DTMOS, which has a very large body effect factor at low threshold voltage and high current drive at low supply voltage.

Two essential technologies for a 3D Solid State Drive (3D-SSD) with a boost converter are presented in this paper. The first topic is the spiral inductor design which determines the performance of the boost converter, and the second is the effect of TSV's on the boost converter. These techniques are very important in achieving a 3D-SSD with a boost converter. In the design of the inductor, the on-board inductor from 250 nH to 320 nH is the best design feature that meets all requirements, including high output voltage above 20 V, fast rise time, low energy consumption, and area smaller than 25 mm2. The use of a boost converter with the proposed inductor leads to a reduction of the energy consumption during the write operation of the proposed 1.8-V 3D-SSD by 68% compared with the conventional 3.3-V 3D-SSD with the charge pump. The feasibility of 3D-SSD's with Through Silicon Vias (TSV's) connections is also discussed. In order to maintain the advantages of the boost converter over the charge pump, the reduction of the parasitic resistance of TSV's is very important.

In this paper, a 0.18-V input three-stage charge pump circuit applying forward body bias is proposed for energy harvesting applications. In the developed charge pump, all the MOSFETs are forward body biased by using the inter-stage/output voltages. By applying the proposed charge pump as the startup in the boost converter, the kick-up input voltage of the boost converter is reduced to 0.18 V. To verify the circuit characteristics, the conventional zero body bias charge pump and the proposed forward body bias charge pump were fabricated with 65 nm CMOS process. The measured output current of the proposed charge pump under 0.18-V input voltage is increased by 170% comparing to the conventional one at the output voltage of 0.5 V. In addition, the boost converter successfully boosts the 0.18-V input to higher than 0.65-V output.

In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5 V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65 nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

Dependence of within-die delay variations on power supply voltage (VDD) is measured down to 0.4 V. The VDD dependence of the within-die delay variation of manual layout and irregular auto place and route (P&R) layout are compared for the first time. The measured relative delay (=sigma/average) variation difference between the manual layout and the P&R layout decreases from 1.56% to 0.07% with reducing VDD from 1.2 V to 0.4 V, because the random delay variations due to the random transistor variations dominate total delay variations instead of the delay variations due to interconnect length variations at low VDD.

An on-chip power supply noise canceller with higher voltage supply and switching transistor is proposed and the effectiveness of the canceller is experimentally verified. The noise canceller is effective for nano-second order noise caused by circuit wakeup or step increase of frequency in frequency hopping. The principle of the noise canceller is to reduce the current flowing through the supply line of VDD by injecting additional current from the higher voltage supply, so that the voltage drop across the VDD supply line is reduced. As additional current flow from higher supply, switching transistor has to be turned off not to increase the power consumption. With turn-off time of 2L/R, this current can be turned off without inducting another droop due to the increase of current flowing through the power supply line. The measurement shows the canceller reduces 68% of the noise with load circuit equivalent to 530 k logic gates in 90-nm CMOS with 9% wire overhead, 1.5% area overhead, and 3% power overhead at 50 k wake-ups/s. Compared to passive noise reduction, proposed noise canceller reduces power supply noise by 64% without wire overhead and to achieve same noise reduction with passive method, 77 times more C or 45 times less L is required. Too large switching transistor results in saturated noise reduction effect and higher power consumption. A rule-of-thumb is to set the on-resistance to supply 100% of load current when turned-on.

A 315 MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40 nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11 µW power consumption at 315 MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4 µW with 7.9 dB noise figure and 20.5 dB gain in state-of-the-art designs.

This paper presents an ultra-low power and temperature-independent voltage detector with a post-fabrication programming method, and presents a theoretical analysis and measurement results. The voltage detector is composed of a programmable voltage detector and a glitch-free voltage detector to realize both programmable and glitch-free operation. The programmable voltage detector enables the programmable detection voltages in the range from 0.52V to 0.85V in steps of less than 49mV. The glitch-free voltage detector enables glitch-free operation when the supply voltage is near 0V. A multiple voltage copier (MVC) in the programmable voltage detector is newly proposed to eliminate the tradeoff between the temperature dependence and power consumption. The design consideration and a theoretical analysis of the MVC are introduced to clarify the relationship between the current in the MVC and the accuracy of the duplication. From the analysis, the tradeoff between the duplication error and the current of MVC is introduced. The proposed voltage detector is fabricated in a 250nm CMOS process. The measurement results show that the power consumption is 248pW and the temperature coefficient is 0.11mV/°C.

An opamp design with outside-rail output relaxing a low-voltage constraint on future scaled transistors is presented. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8-V 0.18-µm standard CMOS process. The 3-V-output operation is experimentally verified. The outside-rail output design with scaled transistors shows area advantage over un-scaled and inside-rail design while keeping signal-to-noise ratio and gain bandwidth constant. The chip area is estimated to be 47% of the conventional opamp using a 0.35-µm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-µm CMOS design due to reduced capacitor area. The proposed design could be extended to n-tuple VDD operation and applied to circuits with a feed back loop such as gain stage and filters. The extendibility of n-tuple VDD operation and its application are discussed with simulation results.

In order to explore the feasibility of large-scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of the minimum operating voltage (VDD min ) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90 nm CMOS ring oscillators (RO's). The measured average VDD min of inverter RO's increased from 90 mV to 343 mV when the number of RO stages increased from 11 to 1 Mega, which indicates the difficulty of VDD scaling in large-scale subthreshold logic circuits. The dependence of VDD min on the number of stages is calculated using the subthreshold current model with random threshold voltage (VTH) variations and compared with the measured results, and the tendency of the measurement is confirmed. The effect of adaptive body bias control to compensate purely random VTH variation is also investigated. Such compensation would require impractical inverter-by-inverter adaptive body bias control.

A low power impulse radio ultra-wideband (IR-UWB) receiver for DC-960 MHz band is proposed in this paper. The proposed receiver employs multiple DC power-free charge-domain sampling correlators to eliminate the need for phase synchronization. To alleviate BER degradation due to an increased charge injection in a subtraction operation in the sampling correlator than that of an addition operation, a comparator with variable threshold (=offset) voltage is used, which enables an addition-only operation. The developed receiver fabricated in 1.2 V 65 nm CMOS achieves the lowest energy consumption of 17.6 pJ/bit at 100 Mbps in state-of-the-art correlation-based UWB receivers.

A 0.6-V voltage shifter and a 0.6-V clocked comparator are presented for sampling correlation-based impulse radio UWB receiver. The voltage shifter is used for a novel split swing level scheme-based CMOS transmission gate which can reduce the power consumption by four times. Compared to the conventional voltage shifter, the proposed voltage shifter can reduce the required capacitance area by half and eliminate the non-overlapping complementary clock generator. The proposed 0.6-V clocked comparator can operate at 100-MHz clock with the voltage shifter. To reduce the power consumption of the conventional continuous-time comparator based synchronization control unit, a novel clocked-comparator based control unit is presented, thereby achieving the lowest energy consumption of 3.9 pJ/bit in the correlation-based UWB receiver with the 0.5 ns timing step for data synchronization.

A capacitive coupling wireless connector circuit is implemented with 50 µm 50 µm pads, which is a 25X reduction of pad size compared with previous wireless connectors by allowing contacting and non-contacting modes. The proposed track and charge scheme allows both contacting and non-contacting communication through PCB capacitive pads. By making the precharge level of the input VDD or VSS, instead of 1/2 VDD, the time necessary to precharge is reduced. The proposed digitally tunable comparator does not require analog voltages, reduces the power to less than 1/20 at lower frequencies compared to previous capacitive coupling receivers. A test chip successfully transmitted and received 1 Gb/s, 27-1PRBS signal at 1 mW while increasing design freedom of the wireless connectors.

In this paper, a novel switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) is proposed with reduced output ripple at variable output voltages. While performing pulse density modulation (PDM), the proposed PDWM modulates the pulse width at the same time to reduce the output ripple with high power efficiency. The prototype chip was implemented using 65 nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional PDM scheme, the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.

This paper presents a new type of electromagnetic interference (EMI) measurement system. An EMI Camera LSI (EMcam) with a 124 on-chip 25050 µm2 loop antenna matrix in 65 nm CMOS is developed. EMcam achieves both the 2D electric scanning and 60 µm-level spatial precision. The down-conversion architecture increases the bandwidth of EMcam and enables the measurement of EMI spectrum up to 3.3 GHz. The shared IF-block scheme is proposed to relax both the increase of power and area penalty, which are inherent issues of the matrix measurement. The power and the area are reduced by 74% and 73%, respectively. EMI measurement with the smallest 3212 µm2 antenna to date is also demonstrated.

A novel DC-to-960 MHz impulse radio ultra-wideband (IR-UWB) transceiver based on threshold detection technique is developed. It features a digital pulse-shaping transmitter, a DC power-free pulse discriminator and an error-recovery phase-frequency detector. The developed transceiver in 90 nm CMOS achieves the lowest energy consumption of 2.2 pJ/bit transmitter and 1.9 pJ/bit receiver at 100 Mbps in the UWB transceivers.