IEICE TRANSACTIONS on Electronics
An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors
Summary :
An opamp design with outside-rail output relaxing a low-voltage constraint on future scaled transistors is presented. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8-V 0.18-µm standard CMOS process. The 3-V-output operation is experimentally verified. The outside-rail output design with scaled transistors shows area advantage over un-scaled and inside-rail design while keeping signal-to-noise ratio and gain bandwidth constant. The chip area is estimated to be 47% of the conventional opamp using a 0.35-µm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-µm CMOS design due to reduced capacitor area. The proposed design could be extended to n-tuple VDD operation and applied to circuits with a feed back loop such as gain stage and filters. The extendibility of n-tuple VDD operation and its application are discussed with simulation results.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.786-792
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.4.786
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
- Category
- Analog and Communications
Authors
Keyword
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Koichi ISHIDA, Atit TAMTRAKARN, Hiroki ISHIKURO, Makoto TAKAMIYA, Takayasu SAKURAI, "An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 4, pp. 786-792, April 2007, doi: 10.1093/ietele/e90-c.4.786.
Abstract: An opamp design with outside-rail output relaxing a low-voltage constraint on future scaled transistors is presented. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8-V 0.18-µm standard CMOS process. The 3-V-output operation is experimentally verified. The outside-rail output design with scaled transistors shows area advantage over un-scaled and inside-rail design while keeping signal-to-noise ratio and gain bandwidth constant. The chip area is estimated to be 47% of the conventional opamp using a 0.35-µm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-µm CMOS design due to reduced capacitor area. The proposed design could be extended to n-tuple VDD operation and applied to circuits with a feed back loop such as gain stage and filters. The extendibility of n-tuple VDD operation and its application are discussed with simulation results.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.786/_p
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@ARTICLE{e90-c_4_786,
author={Koichi ISHIDA, Atit TAMTRAKARN, Hiroki ISHIKURO, Makoto TAKAMIYA, Takayasu SAKURAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors},
year={2007},
volume={E90-C},
number={4},
pages={786-792},
abstract={An opamp design with outside-rail output relaxing a low-voltage constraint on future scaled transistors is presented. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8-V 0.18-µm standard CMOS process. The 3-V-output operation is experimentally verified. The outside-rail output design with scaled transistors shows area advantage over un-scaled and inside-rail design while keeping signal-to-noise ratio and gain bandwidth constant. The chip area is estimated to be 47% of the conventional opamp using a 0.35-µm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-µm CMOS design due to reduced capacitor area. The proposed design could be extended to n-tuple VDD operation and applied to circuits with a feed back loop such as gain stage and filters. The extendibility of n-tuple VDD operation and its application are discussed with simulation results.},
keywords={},
doi={10.1093/ietele/e90-c.4.786},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 786
EP - 792
AU - Koichi ISHIDA
AU - Atit TAMTRAKARN
AU - Hiroki ISHIKURO
AU - Makoto TAKAMIYA
AU - Takayasu SAKURAI
PY - 2007
DO - 10.1093/ietele/e90-c.4.786
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - An opamp design with outside-rail output relaxing a low-voltage constraint on future scaled transistors is presented. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8-V 0.18-µm standard CMOS process. The 3-V-output operation is experimentally verified. The outside-rail output design with scaled transistors shows area advantage over un-scaled and inside-rail design while keeping signal-to-noise ratio and gain bandwidth constant. The chip area is estimated to be 47% of the conventional opamp using a 0.35-µm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-µm CMOS design due to reduced capacitor area. The proposed design could be extended to n-tuple VDD operation and applied to circuits with a feed back loop such as gain stage and filters. The extendibility of n-tuple VDD operation and its application are discussed with simulation results.
ER -
English
