IEICE TRANSACTIONS on Electronics
A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm CMOS for Wireless Sensor Network
Summary :
A 315 MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40 nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11 µW power consumption at 315 MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4 µW with 7.9 dB noise figure and 20.5 dB gain in state-of-the-art designs.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.6 pp.1035-1041
- Publication Date
- 2012/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.1035
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
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Lechang LIU, Takayasu SAKURAI, Makoto TAKAMIYA, "A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm CMOS for Wireless Sensor Network" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 6, pp. 1035-1041, June 2012, doi: 10.1587/transele.E95.C.1035.
Abstract: A 315 MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40 nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11 µW power consumption at 315 MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4 µW with 7.9 dB noise figure and 20.5 dB gain in state-of-the-art designs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1035/_p
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@ARTICLE{e95-c_6_1035,
author={Lechang LIU, Takayasu SAKURAI, Makoto TAKAMIYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm CMOS for Wireless Sensor Network},
year={2012},
volume={E95-C},
number={6},
pages={1035-1041},
abstract={A 315 MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40 nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11 µW power consumption at 315 MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4 µW with 7.9 dB noise figure and 20.5 dB gain in state-of-the-art designs.},
keywords={},
doi={10.1587/transele.E95.C.1035},
ISSN={1745-1353},
month={June},}
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TY - JOUR
TI - A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm CMOS for Wireless Sensor Network
T2 - IEICE TRANSACTIONS on Electronics
SP - 1035
EP - 1041
AU - Lechang LIU
AU - Takayasu SAKURAI
AU - Makoto TAKAMIYA
PY - 2012
DO - 10.1587/transele.E95.C.1035
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2012
AB - A 315 MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40 nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11 µW power consumption at 315 MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4 µW with 7.9 dB noise figure and 20.5 dB gain in state-of-the-art designs.
ER -
English
