With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multiple-input gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32nm PTM model.

Memristor is drawing more and more attraction nowadays after HP Laboratory announced its invention. Since then many researchers are taking efforts to find its applications in various areas of the information technology. Among the important applications, one of the interesting issues is the research on memristor circuits. To put forward such research, there is an urgent demand to establish a memristor SPICE model, such that people could conduct SPICE simulation to obtain the performance of the memristor circuits under their investigation. This paper reports our efforts to meet the urgent demand. Based on the memristor device fabrication technology parameters, as well as the theoretical description on memristor, we first propose memristor SPICE models, then verify the effectiveness of the proposed models by applying it to some memristor circuits. Simulation results are satisfactory.

Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this paper, we present a methodology for determining the parameters that yield the best- and worst-case delays when interconnect structural parameters have the minimum and maximum values with process variations. We also present analysis results of our circuit model using the methodology. The min and max conditions for the time constant are found to be (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh), respectively. Here, +Δ or -Δ means the max or min corner value of each parameter variation, where w is the width, t is the interconnect thickness, and h is the height. Best and worst conditions for delay time are as follows: 1) given a circuit with an optimum driver, dense interconnects, and small branch capacitance, the best and worst conditions are respectively (-Δw, +Δt, +Δh) & (+Δw, +Δt, -Δh), 2) given driver and/or via resistances that are higher than the interconnect resistance, dense interconnects, and small branch capacitance, they are (-Δw, -Δt, +Δh) & (+Δw, +Δt, -Δh), and 3) for other conditions, they are (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh). Moreover, if there must be only one condition each for the best- and worst-case delays, they are (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh).

Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and Ceff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.

The compound element pseudo-transient analysis (PTA) algorithm is an effective practical method for finding the DC operating point when the Newton-Raphson method fails. It is able to effectively prevent from the oscillation problems compared with conventional PTA algorithms. In this paper, an effective SPICE3 implementation method for the compound element PTA algorithm is proposed. It has the characteristic of not expanding the Jacobian matrix and not changing the Jacobian matrix structure when the pseudo-transient numerical simulation is being done. Thus a high simulation efficiency is guaranteed. The ability of the proposed SPICE3 implementation to avoid the oscillation problems and the simulation efficiency are demonstrated by examples.

In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance Ceff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and Ceff in the Thevenin model are not equal. The charge difference between interconnect load and Ceff has the large influence to the accuracy of computing Ceff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and Ceff is considered.

Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.

A low-power sub-1-V self-biased low-voltage reference is proposed for micropower electronic applications based on body effect. The proposed reference has a very low temperature dependence by using a MOSFET with body effect compared with other reported low-power references. An HSPICE simulation shows that the reference voltage and the total power dissipation are 181 mV and 1.1 µW, respectively. The temperature coefficient of the reference voltage is 33 ppm/ at temperatures from -40 to 100. The supply voltage can be as low as 0.95 V in a standard CMOS 0.35 µm technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. Furthermore, the supply voltage dependence is -0.36 mV/V (Vdd=0.95-3.3 V).

The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

The pseudo-transient method is discussed in this paper as one of practical methods to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. The mathematical description for this method is presented and an effective pseudo-transient algorithm utilizing compound pseudo-elements is proposed. Numerical examples are demonstrated to prove that our algorithm is able to avoid the oscillation problems effectively and also improve the simulation efficiency.

Analog multipliers are one of the most important building blocks in analog signal processing circuits. The performance with high linearity and wide input range is usually required for analog four-quadrant multipliers in most applications. Therefore, a highly linear and wide input range four-quadrant CMOS analog multiplier using active feedback is proposed in this paper. Firstly, a novel configuration of four-quadrant multiplier cell is presented. Its input dynamic range and linearity are improved significantly by adding two resistors compared with the conventional structure. Then based on the proposed multiplier cell configuration, a four-quadrant CMOS analog multiplier with active feedback technique is implemented by two operational amplifiers. Because of both the proposed multiplier cell and active feedback technique, the proposed multiplier achieves a much wider input range with higher linearity than conventional structures. The proposed multiplier was fabricated by a 0.6 µm CMOS process. Experimental results show that the input range of the proposed multiplier can be up to 5.6Vpp with 0.159% linearity error on VX and 4.8Vpp with 0.51% linearity error on VY for 2.5V power supply voltages, respectively.

In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.