This letter proposes non-pilot-aided symbol timing and carrier frequency estimation methods in a multicarrier transmission system. To do this, multicarrier system uses a frequency diversity scheme over two consecutive data symbols with the combination of a cyclic time shift. Using the multicarrier signal equipped with frequency diversity, however, time and frequency are accurately estimated without any training symbol.

Non-autoregressive generation has attracted more and more attention due to its fast decoding speed. Latent alignment objectives, such as CTC, are designed to capture the monotonic alignments between the predicted and output tokens, which have been used for machine translation and sentence summarization. However, our preliminary experiments revealed that CTC performs poorly on document abstractive summarization, where a high compression ratio between the input and output is involved. To address this issue, we conduct a theoretical analysis and propose Hierarchical Latent Alignment (HLA). The basic idea is a two-step alignment process: we first align the sentences in the input and output, and subsequently derive token-level alignment using CTC based on aligned sentences. We evaluate the effectiveness of our proposed approach on two widely used datasets XSUM and CNNDM. The results indicate that our proposed method exhibits remarkable scalability even when dealing with high compression ratios.

Radio Frequency based Device-Free Localization (RFDFL) is an emerging localization technique without requirements of attaching any electronic device to a target. The target can be localized by means of measuring the shadowing of received signal strength caused by the target. However, the accuracy of RFDFL deteriorates seriously in environment with WiFi interference. State-of-the-art methods do not efficiently solve this problem. In this paper, we propose a dual-band method to improve the accuracy of RFDFL in environment without/with severe WiFi interference. We introduce an algorithm of fusing dual-band images in order to obtain an enhanced image inferring more precise location and propose a timestamp-based synchronization method to associate the dual-band images to ensure their one-one correspondence. With real-world experiments, we show that our method outperforms traditional single-band localization methods and improves the localization accuracy by up to 40.4% in real indoor environment with high WiFi interference.

This letter proposes a low-complexity scheme for estimating the frequency of a complex sinusoid in flat fading channels. The proposed estimator yields an estimation performance that is comparable to the existing autocorrelation-based frequency estimator, while retaining the same frequency range. Its implementation complexity is much lower than the conventional scheme, thus this allows for fast estimation in real time.

This paper evaluates the performance of a pilot-assisted fine carrier frequency offset (CFO) estimation scheme for orthogonal frequency division multiplexing (OFDM) in time-varying channels. An analytical closed-form expression of the mean square error (MSE), of the post-FFT based CFO synchronization scheme, is presented in terms of time-variant fading channels. To verify our analysis in this paper, simulations are carried out within the framework of mobile WiMAX systems.

Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.

Graph layouts reveal global or local structures of graph data. However, there are few studies on assisting readers in better reconstructing a graph from a layout. This paper attempts to generate a layout whose edges can be reestablished. We reformulate the graph layout problem as an edge classification problem. The inputs are the vertex pairs, and the outputs are the edge existences. The trainable parameters are the laid-out coordinates of the vertices. We propose a binary classification-based graph layout (BCGL) framework in this paper. This layout aims to preserve the local structure of the graph and does not require the total similarity relationships of the vertices. We implement two concrete algorithms under the BCGL framework, evaluate our approach on a wide variety of datasets, and draw comparisons with several other methods. The evaluations verify the ability of the BCGL in local neighborhood preservation and its visual quality with some classic metrics.

Learning semantic representation for translation context is beneficial to statistical machine translation (SMT). Previous efforts have focused on implicitly encoding syntactic and semantic knowledge in translation context by neural networks, which are weak in capturing explicit structural syntax information. In this paper, we propose a new neural network with a tree-based convolutional architecture to explicitly learn structural syntax information in translation context, thus improving translation prediction. Specifically, we first convert parallel sentences with source parse trees into syntax-based linear sequences based on a minimum syntax subtree algorithm, and then define a tree-based convolutional network over the linear sequences to learn syntax-based context representation and translation prediction jointly. To verify the effectiveness, the proposed model is integrated into phrase-based SMT. Experiments on large-scale Chinese-to-English and German-to-English translation tasks show that the proposed approach can achieve a substantial and significant improvement over several baseline systems.

This paper proposes a dual-level low voltage differential signaling (DLVDS) circuit aimed at low power consumption and reducing transmission lines for LCD driver IC's. We apply two-bit binary data to the DLVDS circuit as inputs, and then the circuit converts these two inputs into two kinds of fully differential signal levels. In the DLVDS circuit, two transmission lines are sufficient to transfer two-bit binary inputs while keeping the conventional LVDS features. The receiver recovers the original two-bit binary data through a level decoding circuit. The proposed circuit was fabricated using a commercial 0.25 µm CMOS technology. Under a 2.5 V supply voltage, the circuit shows a data rate of 1-Gbps/2-line and power consumption of 35 mW.

In this paper we propose a novel and efficient method for the optimization of the power/ground (P/G) network in VLSI circuit layouts with reliability constraints. Previous algorithms in the P/G network sizing used the sequence-of-linear-programming (SLP) algorithm to solve the nonlinear optimization problems. However the transformation from nonlinear network to linear subnetwork is not optimal enough. Our new method is inspired by the biological evolution and use the grid-genetic-algorithm (GGA) to solve the optimization problem. Experimental results show that new P/G network sizes are smaller than previous algorithms, as the fittest survival in the nature. Another significant advance is that GGA method can be applied for all P/G network problems because it can get the results directly no matter whether these problems are linear or not. Thus GGA can be adopted in the transient behavior of the P/G network sizing in the future, which recently faces on the obstacles in the solution of the complex nonlinear problems.

This paper presents a simulation based method to predict the amount of frequency interference in a passive type RFID system. To judge occurrence of frequency interference, we use a parameter POI (probability of interference) that depends on several factors such as multiple access method, emission mask, the number of channel, etc. Due to its dependence on several factors, a Monte-carlo based simulation is suitably used. Through the simulation, we draw minimum separation distance between two readers and examine performance degradation due to aggregate interfering readers. Moreover, we present a reader deployment strategy based on the average POI of active readers operating in some area.

This letter presents a new TR-UWB receiver exploiting frequency components of UWB pulses. This is accomplished by separating frequency-components of UWB pulses into real and imaginary parts, independently correlating and effectively combining them. We analytically show this scheme improves the output SNR compared with a conventional one using complex correlation. This will also be justified by simulation results.

In this letter, we propose an integer carrier frequency offset (IFO) estimator in the presence of symbol timing error for an ultra-wideband multi-band orthogonal frequency division multiplexing (UWB MB-OFDM) system. The proposed IFO estimator uses frequency-domain spreaded data symbol which is provided in the MB-OFDM system. To demonstrate the accuracy of the proposed IFO estimator, comparisons are made with conventional estimators via computer simulation.

Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

A digital background calibration technique using signal-dependent dithering is proposed, to correct the nonlinear errors which results from capacitor mismatches and finite opamp gain in pipelined analog-to-digital converter (ADC). Large magnitude dithers are used to measure and correct both errors simultaneously in background. In the proposed calibration system, the 2.5-bit capacitor-flip-over multiplying digital-to-analog converter (MDAC) stage is modified for the injection of large magnitude dithering by adding six additional comparators, and thus only three correction parameters in every stage subjected to correction were measured and extracted by a simple calibration algorithm with multibit first stage. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio improves from 63.3 to 79.3dB and the spurious-free dynamic range is increased from 63.9 to 96.4dB after calibrating the first two stages, in a 14-bit 100-MS/s pipelined ADC with σ=0.2% capacitor mismatches and 60dB nonideal opamp gain. The time of calibrating the first two stages is around 1.34 seconds for the modeled ADC.

This paper proposes a new algorithm for substring searching. Our algorithm is an improvement on the famous BM algorithm. When a mismatch happens while searching a substring (pattern), the BM algorithm will use two strategies to calculate shifting distances of the substring respectively and selects the larger one. In comparison, our algorithm uses each of the two strategies for their most suitable cases separately without a selection operation. Experimental results demonstrated that our algorithm is more efficient than the BM algorithm and the Quick Search algorithm, especially for binary strings and DNA strings.

This paper proposes an efficient two-scan labeling algorithm for binary hexagonal images. Unlike conventional labeling algorithms, which process pixels one by one in the first scan, our algorithm processes pixels two by two. We show that using our algorithm, we can check a smaller number of pixels. Experimental results demonstrated that our method is more efficient than the algorithm extended straightly from the corresponding labeling algorithm for rectangle binary images.

This paper proposes a graph-theory-based Euler number computing algorithm. According to the graph theory and the analysis of a mask's configuration, the Euler number of a binary image in our algorithm is calculated by counting four patterns of the mask. Unlike most conventional Euler number computing algorithms, we do not need to do any processing of the background pixels. Experimental results demonstrated that our algorithm is much more efficient than conventional Euler number computing algorithms.

This paper proposes an efficient design algorithm for power/ground (P/G) network synthesis with dynamic signal consideration, which is mainly caused by Ldi/dt noise and Cdv/dt decoupling capacitance (DECAP) current in the distribution network. To deal with the nonlinear global optimization under synthesis constraints directly, the genetic algorithm (GA) is introduced. The proposed GA-based synthesis method can avoid the linear transformation loss and the restraint condition complexity in current SLP, SQP, ICG, and random-walk methods. In the proposed Hybrid Grid Synthesis algorithm, the dynamic signal is simulated in the gene disturbance process, and Trapezoidal Modified Euler (TME) method is introduced to realize the precise dynamic time step process. We also use a hybrid-SLP method to reduce the genetic execute time and increase the network synthesis efficiency. Experimental results on given power distribution network show the reduction on layout area and execution time compared with current P/G network synthesis methods.