This paper proposes a dual-level low voltage differential signaling (DLVDS) circuit aimed at low power consumption and reducing transmission lines for LCD driver IC's. We apply two-bit binary data to the DLVDS circuit as inputs, and then the circuit converts these two inputs into two kinds of fully differential signal levels. In the DLVDS circuit, two transmission lines are sufficient to transfer two-bit binary inputs while keeping the conventional LVDS features. The receiver recovers the original two-bit binary data through a level decoding circuit. The proposed circuit was fabricated using a commercial 0.25 µm CMOS technology. Under a 2.5 V supply voltage, the circuit shows a data rate of 1-Gbps/2-line and power consumption of 35 mW.

This paper presents a simulation based method to predict the amount of frequency interference in a passive type RFID system. To judge occurrence of frequency interference, we use a parameter POI (probability of interference) that depends on several factors such as multiple access method, emission mask, the number of channel, etc. Due to its dependence on several factors, a Monte-carlo based simulation is suitably used. Through the simulation, we draw minimum separation distance between two readers and examine performance degradation due to aggregate interfering readers. Moreover, we present a reader deployment strategy based on the average POI of active readers operating in some area.

This letter presents a new TR-UWB receiver exploiting frequency components of UWB pulses. This is accomplished by separating frequency-components of UWB pulses into real and imaginary parts, independently correlating and effectively combining them. We analytically show this scheme improves the output SNR compared with a conventional one using complex correlation. This will also be justified by simulation results.

In this letter, we propose an integer carrier frequency offset (IFO) estimator in the presence of symbol timing error for an ultra-wideband multi-band orthogonal frequency division multiplexing (UWB MB-OFDM) system. The proposed IFO estimator uses frequency-domain spreaded data symbol which is provided in the MB-OFDM system. To demonstrate the accuracy of the proposed IFO estimator, comparisons are made with conventional estimators via computer simulation.

This letter proposes a low-complexity estimation method of integer frequency offset in orthogonal frequency division multiplexing (OFDM) systems. The performance and complexity of the proposed method are compared with that of Morelli and Mengali's method based on maximum likelihood (ML) technique. The results show that the performance of the proposed method is comparable to that of M&M method with reduced complexity.

This letter proposes non-pilot-aided symbol timing and carrier frequency estimation methods in a multicarrier transmission system. To do this, multicarrier system uses a frequency diversity scheme over two consecutive data symbols with the combination of a cyclic time shift. Using the multicarrier signal equipped with frequency diversity, however, time and frequency are accurately estimated without any training symbol.

This letter proposes a low-complexity scheme for estimating the frequency of a complex sinusoid in flat fading channels. The proposed estimator yields an estimation performance that is comparable to the existing autocorrelation-based frequency estimator, while retaining the same frequency range. Its implementation complexity is much lower than the conventional scheme, thus this allows for fast estimation in real time.

This paper evaluates the performance of a pilot-assisted fine carrier frequency offset (CFO) estimation scheme for orthogonal frequency division multiplexing (OFDM) in time-varying channels. An analytical closed-form expression of the mean square error (MSE), of the post-FFT based CFO synchronization scheme, is presented in terms of time-variant fading channels. To verify our analysis in this paper, simulations are carried out within the framework of mobile WiMAX systems.

A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.