In this Letter, an analytic method to calculate the cumulative distribution function (cdf) of the cell sojourn time with various distributions of a mobile velocity (constant, uniform, or Gaussian distribution) is presented. Gaussian pdf and cdf are estimated through curve-fitting. The cdf of the cell sojourn time is calculated through a numerical method. It is shown that the simulated result matches very close to the calculated result.

In this letter, we investigate a decimated selective mapping (SLM) method for the peak-to-mean envelope power ratio (PMEPR) reduction in an OFDM system. Under the condition of the same side information (SI) bits, the SLM can be implemented by decimating OFDM samples, which is less complex compared to the ordinary SLM incurring a slight degradation of the PMEPR performance. The decimated SLM (DSLM) approach can be generalized to a multiple-antenna OFDM system employing a space-time block coding (STBC).

A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.

The multiple registration schemes (MRSs) proposed here are classified into 3 cases by combining five registration schemes which are power up registration scheme (PURS), power down registration scheme (PDRS), zone based registration scheme (ZBRS), distance based registration scheme (DBRS), and implicit registration scheme (IRS) as follows: the first is MRS1 which covers PURS, PDRS, and ZBRS; the second is MRS2 which covers PURS, PDRS, and DBRS; the third is MRS3 which covers PURS, PDRS, IRS, and DBRS. The three proposed schemes are compared each other by analyzing their combined signaling traffic of paging and registration with considering various parameters of a mobile station behavior (unencumbered call duration, power up and down rate, velocity, etc.). Also, we derive allowable location areas from which the optimal location area is obtained. Numerical results show that MRS3 yields better performance than ZBRS, DBRS, MRS1, and MRS2 in most cases of a mobile station behavior, and it has an advantage of distributing the load of signaling traffic into every cell, which is important in personal communication system.

As the code division multiple access (CDMA) based third generation cellular infrastructure requires high performance signal processing in a baseband modem, an application-specific integrated circuit or a field-programmable gate array has commonly been used for chip rate processing. In this paper, the use of digital signal processors (DSP) is explored for a cdma2000 and a wideband CDMA channel modem with the goal of increasing flexibility. The design concepts of the prototype software-defined radio platform we implemented to estimate the potential and feasibility of commercial SDR platforms are presented. We discuss the hardware and software architecture of the platform, considerations for reconfigurability, and the test results. We also address practical issues for real-time chip rate processing and optimization schemes of DSP software, and provide detailed measurement results of DSP performance.

This paper presents a hybrid decimal division algorithm to improve division speed. The proposed hybrid algorithm employs either non-restoring or restoring algorithm on each digit to reduce iterative computations. The selection of the algorithm is based on the relative remainder values with respect to the half of its divisor. The proposed algorithm requires maximum 7n+4 add/subtract operations for an n-digit quotient, whereas other restoring or non-restoring schemes comprise more than 10n+1 operations.

This paper proposes a dual-level low voltage differential signaling (DLVDS) circuit aimed at low power consumption and reducing transmission lines for LCD driver IC's. We apply two-bit binary data to the DLVDS circuit as inputs, and then the circuit converts these two inputs into two kinds of fully differential signal levels. In the DLVDS circuit, two transmission lines are sufficient to transfer two-bit binary inputs while keeping the conventional LVDS features. The receiver recovers the original two-bit binary data through a level decoding circuit. The proposed circuit was fabricated using a commercial 0.25 µm CMOS technology. Under a 2.5 V supply voltage, the circuit shows a data rate of 1-Gbps/2-line and power consumption of 35 mW.

This paper describes the design, implementation and testing of wideband code division multiple access (CDMA) base station demodulator for the international mobile telecommunication-2000 (IMT-2000) system test plant based on cdma2000 radio transmission technology (RTT). The performance of the implemented base station demodulator is measured and compared with the theoretical performance bound. The system test plant equipped with this demodulator provides wireless services, such as high quality speech (9.6 kbps), real-time video (384 kbps) and internet protocol (IP) based data services (144 kbps) in a mobile radio environment.

This paper describes a 32-bit fully asynchronous microprocessor, with 4-stage pipeline based on a RISC-like architecture. Issues relevant to the processor such as design of self-timed datapath, asynchronous controller and interconnection circuits are discussed. Simulation results are included using parameters extracted from layout, which showed about the 300 MIPS processing speed and used 71,000 transistors with 0.5 µm CMOS technology.

In this paper, we design and implement a fast asynchronous embedded CISC microprocessor, A8051, introducing well-tuned pipeline architecture and enhanced control schemes. This work shows an asynchronous design methodology for a CISC type processor, handling the complicated control structure and various instructions. We tuned the proposed architecture to the 5-stage pipeline, reducing the number of idle stages. For the work, we regrouped the instructions based on the number of the machine cycles identified. A8051 has three enhanced control features to improve the system performance: multi-looping control of the pipeline stage, variable length instruction register to get a multiple word instruction in a time, and branch prediction accelerating. The proposed A8051 was synthesized to a gate level design using a 0.35 µm CMOS standard cell library. Simulation results indicate that A8051 provides about 18 times higher speed than the traditional Intel 8051 and about 5 times higher speed than the previously designed asynchronous 8051. In power consumption, core of A8051 shows 15 times higher MIPS/Watt than the synchronous H8051.

This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an on-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool.

In this letter, we propose the reducing method of feedback information for transmitting adaptable data rate in multi-user OFDMA/FDD system. In order to transmit the downlink channel information to Base-Station (BS) by using the limited uplink control channel, the proposed algorithm uses the channel variation level which describes the similarity among the adjacent clusters and uses just one modulation and coding scheme (MCS) level which represents the channel information of all clusters. The performance was investigated in one-cellular environment. It has a similar overhead for feedback information with conventional algorithm and has better performance than the conventional algorithm.

We propose a novel paging scheme with a variable paging interval for low power consumption and/or short paging delay. The proposed scheme is based on the fact that packet arrivals during a session follow the characteristics of self-similar process for Http service, while session arrival statistics can be modeled as the Poisson process. The adjustment of paging period provides a useful solution for efficient paging to the UE in the dormant state on packet-switched cellular networks, even though the paging performance is strongly dependent on the traffic arrival model.

An analytic traffic model is presented to estimate the soft handoff rate in DS-CDMA cellular systems. The model is based on the fact that a mobile in soft handoff call is connected to two cell sites when it is in an overlapped region. The handoff rate is estimated by the mobility of mobiles, which is a function of the size and shape of cell area, and the call density and speed of mobiles in the area. Simulation results show good agreement with the analytical model.

Among the broadband wireless communication standards utilized to satisfy the demand for multimedia services, time division duplexing (TDD) is satisfactory for the asymmetric data transmission emphasized in Internet services. In this system, the transition between receiving a frame and transmitting a response must be bounded for an effective use of radio resources. However, the minimized inter-frame space-time requires high processing power. The aim of the present paper is to gain insight into the time latency at the turn-around time of a TDD operation. We also propose a simplified new processor, which is a terminal device-friendly architecture that includes prediction and preparation to support processing of burst-type traffic.

This paper presents a new parallel architecture of syndrome generator for a high-speed BCH (Bose-Chaudhuri-Hocquenghem) decoder. In particular, the proposed parallel syndrome generators are based on LFSR (linear feedback shift register) architecture to achieve high throughput without significant area overhead. From the experimental results, the proposed approach achieves 4.60 Gbps using 0.25-µm standard CMOS technology. This result is much faster than the conventional byte-wise GFM-based counterpart. The high throughputs are due to the well-tuned hardware implementation using unfolding transformation.