This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an on-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Hyun LEE, Je-Hoon LEE, Kyoung-Rok CHO, "Performance and Power Modeling of On-Chip Bus System for a Complex SoC" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 10, pp. 1525-1535, October 2010, doi: 10.1587/transele.E93.C.1525.
Abstract: This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an on-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1525/_p
Copy
@ARTICLE{e93-c_10_1525,
author={Hyun LEE, Je-Hoon LEE, Kyoung-Rok CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Performance and Power Modeling of On-Chip Bus System for a Complex SoC},
year={2010},
volume={E93-C},
number={10},
pages={1525-1535},
abstract={This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an on-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool.},
keywords={},
doi={10.1587/transele.E93.C.1525},
ISSN={1745-1353},
month={October},}
Copy
TY - JOUR
TI - Performance and Power Modeling of On-Chip Bus System for a Complex SoC
T2 - IEICE TRANSACTIONS on Electronics
SP - 1525
EP - 1535
AU - Hyun LEE
AU - Je-Hoon LEE
AU - Kyoung-Rok CHO
PY - 2010
DO - 10.1587/transele.E93.C.1525
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2010
AB - This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an on-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool.
ER -