Hydrogenated polymorphous Silicon allows to fabricate TFTs with very interesting characteristics including better threshold voltage stability than a-Si TFTs, lower leakage current than µc-Si:H TFTs and excellent uniformity. Investigation of threshold voltage shift mechanisms of pm-Si:H TFTs has shown a specific semiconductor material degradation with different activation energies compared to a-Si:H TFTs. TEM analysis has evidenced for the first time a significant structural difference between pm-Si:H and a-Si:H materials, in the TFT device configuration. Pm-Si:H appears to be very suitable for low cost and high performance AM-OLED fabrication.

Crystallization of amorphous silicon on oxide semiconductors using rapid-thermal annealing in vacuum is investigated. A 30 nm n-type amorphous silicon (a-Si) is deposited on zinc-oxide (ZnO) and aluminum doped zinc-oxide (ZnO:Al) by PECVD on glass substrate. Rapid-thermal annealing for 30 min to 180 min of a-Si on ZnO and ZnO:Al were performed at 600. It is found that crystallization of a-Si on oxide semiconductors can be done in shorter time than that of standard solid-phase crystallization (SPC) of amorphous silicon on glass substrate at 600. It has been verified using Raman spectroscopy that a-Si on ZnO:Al changes into polycrystalline silicon (poly-Si) in 30 min at 600.

Opto-Thermal analysis of Semiconductor Blue-Multi-Laser-Diode Annealing (BLDA) for amorphous Si (a-Si) film is conducted by varying the irradiation power, the scanning velocity and the beam shape of blue-laser of 445 nm. Thermal profiles, maximum temperature of the a-Si film and the melting duration are evaluated. By comparing the simulated results with the experimental results, the excellent controllability of BLDA for arbitrary grain size can be explained consistently by the relation between irradiation time and melting duration. The results are useful to estimate poly-crystallized phase such as micro-polycrystalline Si, polycrystalline Si and anisotropic lateral growth of single-crystal-like Si.

Oxide material can make transparent devices with transparent electrodes. We developed a transparent oscillator and rectifier circuits with oxide TFTs. The source/drain and gate electrodes were made by indium thin oxide (ITO), and active layer made by transparent material of IGZO (Indium Gallium Zinc Oxide) on a glass substrate. The RC oscillator was composed of bootstrapped inverters, and 813 kHz oscillation frequency was accomplished at V_DD = 15 V. For DC voltage generation from RF, transparent rectifier was fabricated and evaluated. This DC voltage from rectifier powered to the oscillator which operated successfully to create RF. For data transmission, RF transmission was evaluated with RF from the transparent oscillator. An antenna was connected to the oscillator and RF transmission to a receiving antenna was verified. Through this transmission antenna, RF was transmitted to a receiving antenna successfully. For transparent system of RFID, transparent antenna was developed and verified sending and receiving of data.

Ba_0.5Sr_0.5Ta₂O₆ (BSTA) thin film was successfully fabricated on a Pt/SiO₂/TiO₂/Si substrate using the Sol-Gel method. Fundamental electrical properties of the BSTA thin film were investigated using metal-insulator-metal (MIM) structure. No diffusion of ions, from the thin film or the substrate, is observed because of the using of MIM structure. The Root Mean Square roughness of 1.04 nm shows that thin film grew well on the substrate. The BSTA thin film shows a much higher dielectric constant of about 130 than conventional gate insulators and high-k materials that are currently used in Thin Film Transistors. Low leakage current density of about 10^-8 A/cm² was obtained at an applied electric field of 500 kV/cm. Schottky emission is the dominant conduction mechanism at applied electric fields lower than 500 kV/cm and Fowler-Nordheim tunneling is the dominant conduction mechanism at higher applied electric fields. The Schottky barrier height between the Pt electrode and the Ba_0.5Sr_0.5Ta₂O₆ thin film was estimated to be 0.75 eV.

Effects of atomic hydrogen annealing (AHA) on the film properties and the electrical characteristics of pentacene organic thin-film transistors (OTFTs) are investigated. The surface energy of SiO₂ surface and grain size of pentacene film were decreased with increasing AHA treatment time. For the treatment time of 300 s, pentacene film showed the (00l) and (011') orientation and high carrier mobility in spite of small crystal grain.

This paper describes the design methodology of a low dropout regulator (LDO). It was used to develop a power management sub-system IC for CDMA handsets which is also described in this paper. This IC contains 11 LDOs, bandgap reference, battery charger, control logic and some other peripheral circuits. For CDMA applications, very small ground current in the order of µA in standby mode is required for LDOs. An LDO architecture to meet this requirement and achieve stable operation over the process variation was developed. The on-chip logic efficiently controls all LDOs and battery charger to reduce the power dissipation as much as possible. This mixed signal subsystem has been implemented in the in-house 0.6-µm BCDMOS process. The very low LDO ground current down to 3 µA has been achieved with stable operation.

This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an on-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool.

A resistive feedback-based inductive source degeneration ultra-wideband (UWB) CMOS low noise amplifier (LNA) with floating n-well terminals has been proposed. The resistive feedback technique provides wideband input matching with a small amount of noise degradation by reducing the quality factor of the input resonant circuit. In addition, all n-wells terminals of the triple-well RF transistors are connected to the supply voltage through high value resistors in order to reduce unwanted parasitic capacitances, leading to improvement of the RF performance of the proposed LNA. The proposed UWB LNA is implemented in 0.13 µm CMOS technology and all inductors are fully integrated in this work. Measurement results show a power gain of 10 dB from 3 GHz to 6 GHz, a minimum (maximum) noise figure of 2.3 dB (3.8 dB), an input return loss of better than -8 dB, and an input referred IP3 of -7 dBm. The fabricated chip consumes only 5 mA from a 1.5 V supply voltage.

CMOS SoCs can reduce power consumption by adopting voltage scaling (VS) technologies, where the level converter (LC) is required between voltage domains to avoid dc current. However, the LC often induces high delay penalty and usually results in non-balanced rise and fall delays. Therefore, the performance of the LC strongly affects the effectiveness of VS technologies. In this paper, heuristic sizing methodology for designing a state-of-the-art LC is developed and proposed. Using the proposed methodology, we can design the LC to achieve high performance with balanced rise and fall delay times in a deterministic way.

For the modeling of power amplifiers (PAs) using sub-Nyquist-rate sampling (sub-sampling), a quadratic down-converting architecture with a parallel-cascade method is suggested. Its performance was analyzed regarding the sampling rate below the input Nyquist rate. As a result, the model from the sub-sampling below the input Nyquist rate characterized long-term memory effects whereas the memoryless model could not. The measurement results from RF PAs with the mWiMAX signal verified the modeling performance of this architecture. Also, for the modeling of memoryless PAs, it was shown that this sub-sampled model is still effective regardless of the sampling rate.

An analytical method to make a trade off between tuning range and differential non-linearity (DNL) for a digitally controlled oscillator (DCO) is proposed. To verify the approach, a 12 bit DCO is designed, implemented in 0.18 µm CMOS technology, and tested. The measured DNL was -0.41 Least Significant Bit (LSB) without degrading other parameters which is the best so far among the reported DCOs.

We proposed a novel representation of the thermal noise for scaled MOSFETs by applying an extended van der Ziel's model. A comparison between the proposed representation and Pospieszalski's model is also performed. We confirmed that the representation of drain noise temperature, T_d corresponds to the electron temperature in a gradual channel region.