1-3hit |
Masataka MINAMI Nagatoshi OHKI Hiroshi ISHIDA Toshiaki YAMANAKA Akihiro SHIMIZU Koichiro ISHIBASHI Akira SATOH Tokuo KURE Takashi NISHIDA Takahiro NAGANO
A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less than 1-µm spacing between the n and pMOSFETs is achieved by using a retrograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-µm n-gate load pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-µm p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etching using a plasma-TEOS silicone-dioxide mask. The newly developed memory cell was demonstrated using 0.25-µm CMOS process technology. A 6.93-µm2 and 1-V operation full CMOS SRAM cell with a high-performance circuit was achieved by a simple fabrication process.
Li LU Masahiro ECHIZEN Takashi NISHIDA Kiyoshi UCHIYAMA Yukiharu URAOKA
Ba0.5Sr0.5Ta2O6 (BSTA) thin film was successfully fabricated on a Pt/SiO2/TiO2/Si substrate using the Sol-Gel method. Fundamental electrical properties of the BSTA thin film were investigated using metal-insulator-metal (MIM) structure. No diffusion of ions, from the thin film or the substrate, is observed because of the using of MIM structure. The Root Mean Square roughness of 1.04 nm shows that thin film grew well on the substrate. The BSTA thin film shows a much higher dielectric constant of about 130 than conventional gate insulators and high-k materials that are currently used in Thin Film Transistors. Low leakage current density of about 10-8 A/cm2 was obtained at an applied electric field of 500 kV/cm. Schottky emission is the dominant conduction mechanism at applied electric fields lower than 500 kV/cm and Fowler-Nordheim tunneling is the dominant conduction mechanism at higher applied electric fields. The Schottky barrier height between the Pt electrode and the Ba0.5Sr0.5Ta2O6 thin film was estimated to be 0.75 eV.
Koichiro ISHIBASHI Koichi TAKASUGI Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Toshiaki YAMANAKA Akira FUKAMI Naotaka HASHIMOTO Nagatoshi OHKI Akihiro SHIMIZU Takashi HASHIMOTO Takahiro NAGANO Takashi NISHIDA
A 4-Mb CMOS SRAM with 3.84 µm2 TFT load cells is fabricated using 0.25-µm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.