IEICE TRANSACTIONS on Electronics
A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers
Summary :
A 4-Mb CMOS SRAM with 3.84 µm2 TFT load cells is fabricated using 0.25-µm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E78-C No.6 pp.728-734
- Publication Date
- 1995/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
- Category
Authors
Koichiro ISHIBASHI
Koichi TAKASUGI
Kunihiro KOMIYAJI
Hiroshi TOYOSHIMA
Toshiaki YAMANAKA
Akira FUKAMI
Naotaka HASHIMOTO
Nagatoshi OHKI
Akihiro SHIMIZU
Takashi HASHIMOTO
Takahiro NAGANO
Takashi NISHIDA
Keyword
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Koichiro ISHIBASHI, Koichi TAKASUGI, Kunihiro KOMIYAJI, Hiroshi TOYOSHIMA, Toshiaki YAMANAKA, Akira FUKAMI, Naotaka HASHIMOTO, Nagatoshi OHKI, Akihiro SHIMIZU, Takashi HASHIMOTO, Takahiro NAGANO, Takashi NISHIDA, "A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 6, pp. 728-734, June 1995, doi: .
Abstract: A 4-Mb CMOS SRAM with 3.84 µm2 TFT load cells is fabricated using 0.25-µm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_6_728/_p
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@ARTICLE{e78-c_6_728,
author={Koichiro ISHIBASHI, Koichi TAKASUGI, Kunihiro KOMIYAJI, Hiroshi TOYOSHIMA, Toshiaki YAMANAKA, Akira FUKAMI, Naotaka HASHIMOTO, Nagatoshi OHKI, Akihiro SHIMIZU, Takashi HASHIMOTO, Takahiro NAGANO, Takashi NISHIDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers},
year={1995},
volume={E78-C},
number={6},
pages={728-734},
abstract={A 4-Mb CMOS SRAM with 3.84 µm2 TFT load cells is fabricated using 0.25-µm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers
T2 - IEICE TRANSACTIONS on Electronics
SP - 728
EP - 734
AU - Koichiro ISHIBASHI
AU - Koichi TAKASUGI
AU - Kunihiro KOMIYAJI
AU - Hiroshi TOYOSHIMA
AU - Toshiaki YAMANAKA
AU - Akira FUKAMI
AU - Naotaka HASHIMOTO
AU - Nagatoshi OHKI
AU - Akihiro SHIMIZU
AU - Takashi HASHIMOTO
AU - Takahiro NAGANO
AU - Takashi NISHIDA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1995
AB - A 4-Mb CMOS SRAM with 3.84 µm2 TFT load cells is fabricated using 0.25-µm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.
ER -
English
