An MPEG2 video decoder LSI fully compliant with MPEG2 main profile at main level is described. The video decoder LSI is a single chip solution which can implement MPEG2 video decoding with conventional DRAMs. The LSI features an architecture based on dedicated decoding hardware so as to gain the necessary computational power for real-time processing of ITU-R R.601 size video. The variable length decoder (VLD), owing to our "one symbol decoding in one cycle" policy and a special circuit for detecting unique startcodes, achieved bitstream decoding up to 18 Mbps with a normal decoding process. It also realized fast searching for the next start-code in the picture skipping and error recovery processes. The video decoder LSI also features a hierarchical and adaptive control mechanism. This control mechanism decreases the dead time of the decoding circuits and raises the efficiency of data transfer via the local DRAM port. It also contributes to the realization of error concealment and error recovery processes. This chip is capable of processing NTSC-resolution video depicted in MPEG2 MP＠ML in real-time at 27 MHz operation. The chip integrates about 1200 K transistors using 0.5 µm double metal CMOS technology. The feature of the hardware based architecture results in a low power dissipation, and the chip consumes a 1.4 W of power at 3.3 V supply voltage and is housed in a plastic QFP.

An 18-kb RAM with 9-kgate control logic gates operating during a cycle-time of 1.5 ns has been developed. A pseudo-dual-port RAM function is achieved by a two-bank structure and on-chip control logic. Each bank can operate individually with different address synchronizing the single clock. A sense-amplifier with a selector function reduces the reading propagation time. Bonded SOI wafers reduce the memory-cell capacitance, and this results in a fast write cycle without sacrificing α-particle immunity. The chip is fabricated in a double polysilicon self-aligned bipolar process using trench isolation. The minimum emitter size is 0.52 µm2 and the chip size is 1111 mm2.

A new BiCMOS process based on a high-speed bipolar process with 0.5 µm emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.

New test structures for evaluating isolation capacitance (CTS) and isolation breakdown voltage (BVCCO) have been developed. Using these test structures, we examined the scaling limit of the width and the structure of narrow isolation U-grooves for high-speed and high-density LSIs. We separated the capacitance CTS into two components, CTSS (bottom component) and CTSL (peripheral component), and analyzed the effect of the device structure (isolation width and filling materials) on CTS. We found that the minimum width of the isolation U-groove is especially limited by the increased isolation capacitance between the neighboring N+ buried layers. The minimum width is about 0.3 µm even when SiO2 is used as a filling material. So we developed an effective method to overcome this limitation. Use of a double-trench structure and/or an SOI substrate meet the requirement. A double-trench structure can reduce CTS by more than 50%, while SOI substrates gives reduced CTS, high BVCCO, high α-ray immunity, and reduced process steps.

A low power MPEG-4 video codec LSI with the capability for core profile decoding is presented. A 16-b DSP with a vector pipeline architecture and a 32-b arithmetic unit, eight dedicated hardware engines to accelerate MPEG-4 SP@L1 codec, CP@L1 decoding and post video processing, 20-Mb embedded DRAM, and three peripheral blocks are integrated together on a single chip. MPEG-4 SP@L1 codec, CP@L1 decoding and post video processing are realized with a hybrid architecture consisting of a programmable DSP and dedicated hardware engines at low operating frequency. In order to reduce the power consumption, clock gating technique is fully adopted in each hardware block and embedded DRAM is employed. The chip is implemented using 0.18-µm quad-metal CMOS technology, and its die area is 8.8 mm 8.6 mm. The power consumption is 90 mW at a SP@L1 codec and 110 mW at a CP@L1 decoding.

A 4-Mb CMOS SRAM with 3.84 µm2 TFT load cells is fabricated using 0.25-µm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.

This paper presents a performance evaluation of NAK-based reliable multicast communication protocols operating in an environment where end-to-end delay are heterogeneous. In the case of heterogeneous delay, performance of a timer-based retransmission control scheme may become worse. We show that a counter-based retransmission control scheme works well in the case of heterogeneous transmission delay. We also compare two NAK-based protocols and show that a NAK-multicasting protocol outperforms a NAK-unicasting protocol from the viewpoint of scalability even when delays are heterogeneous.

In reliable multicast communications, retransmission control plays an important role from the viewpoint of scalability. Previous works show that the implosion of control packets, e.g. ACKs or NAKs, degrades the total performance of reliable multicast communications. Local recovery which enables receivers receiving a packet successfully to initiate recovering a lost packet may have the possibility to solve this scalability problem. This paper presents the performance evaluation of local recovery caused by grouping receiving nodes in reliable multicast communication. There seems to be many features dominating the performance of local recovery, the number of nodes in a group, the shared loss occurring simultaneously at multiple receivers and so on. When the number of receivers in a group increases, the geographical expansion of a group will degrade the delay performance of the receivers. In a configuration where most nodes in a local-recovery group suffer from shared loss, the failure of local recovery degrades the total performance. Our simulation results under a hierarchical network topology like the real Internet show that a local-recovery group configuration with two-adjacent MANs grouping performs well.