New Test Structures for Evaluating the Scaling Limit of a Narrow U-Groove Isolation Structure

Yoichi TAMAKI; Takashi HASHIMOTO

New Test Structures for Evaluating the Scaling Limit of a Narrow U-Groove Isolation Structure

Yoichi TAMAKI, Takashi HASHIMOTO

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New test structures for evaluating isolation capacitance (C_TS) and isolation breakdown voltage (BV_CCO) have been developed. Using these test structures, we examined the scaling limit of the width and the structure of narrow isolation U-grooves for high-speed and high-density LSIs. We separated the capacitance C_TS into two components, C_TSS (bottom component) and C_TSL (peripheral component), and analyzed the effect of the device structure (isolation width and filling materials) on C_TS. We found that the minimum width of the isolation U-groove is especially limited by the increased isolation capacitance between the neighboring N⁺ buried layers. The minimum width is about 0.3 µm even when SiO₂ is used as a filling material. So we developed an effective method to overcome this limitation. Use of a double-trench structure and/or an SOI substrate meet the requirement. A double-trench structure can reduce C_TS by more than 50%, while SOI substrates gives reduced C_TS, high BV_CCO, high α-ray immunity, and reduced process steps.

Publication: IEICE TRANSACTIONS on Electronics Vol.E82-C No.4 pp.612-617

Publication Date: 1999/04/25

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Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures)

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Yoichi TAMAKI, Takashi HASHIMOTO, "New Test Structures for Evaluating the Scaling Limit of a Narrow U-Groove Isolation Structure" in IEICE TRANSACTIONS on Electronics, vol. E82-C, no. 4, pp. 612-617, April 1999, doi: .
Abstract: New test structures for evaluating isolation capacitance (C_TS) and isolation breakdown voltage (BV_CCO) have been developed. Using these test structures, we examined the scaling limit of the width and the structure of narrow isolation U-grooves for high-speed and high-density LSIs. We separated the capacitance C_TS into two components, C_TSS (bottom component) and C_TSL (peripheral component), and analyzed the effect of the device structure (isolation width and filling materials) on C_TS. We found that the minimum width of the isolation U-groove is especially limited by the increased isolation capacitance between the neighboring N⁺ buried layers. The minimum width is about 0.3 µm even when SiO₂ is used as a filling material. So we developed an effective method to overcome this limitation. Use of a double-trench structure and/or an SOI substrate meet the requirement. A double-trench structure can reduce C_TS by more than 50%, while SOI substrates gives reduced C_TS, high BV_CCO, high α-ray immunity, and reduced process steps.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_4_612/_p

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@ARTICLE{e82-c_4_612,
author={Yoichi TAMAKI, Takashi HASHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={New Test Structures for Evaluating the Scaling Limit of a Narrow U-Groove Isolation Structure},
year={1999},
volume={E82-C},
number={4},
pages={612-617},
abstract={New test structures for evaluating isolation capacitance (C_TS) and isolation breakdown voltage (BV_CCO) have been developed. Using these test structures, we examined the scaling limit of the width and the structure of narrow isolation U-grooves for high-speed and high-density LSIs. We separated the capacitance C_TS into two components, C_TSS (bottom component) and C_TSL (peripheral component), and analyzed the effect of the device structure (isolation width and filling materials) on C_TS. We found that the minimum width of the isolation U-groove is especially limited by the increased isolation capacitance between the neighboring N⁺ buried layers. The minimum width is about 0.3 µm even when SiO₂ is used as a filling material. So we developed an effective method to overcome this limitation. Use of a double-trench structure and/or an SOI substrate meet the requirement. A double-trench structure can reduce C_TS by more than 50%, while SOI substrates gives reduced C_TS, high BV_CCO, high α-ray immunity, and reduced process steps.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - New Test Structures for Evaluating the Scaling Limit of a Narrow U-Groove Isolation Structure
T2 - IEICE TRANSACTIONS on Electronics
SP - 612
EP - 617
AU - Yoichi TAMAKI
AU - Takashi HASHIMOTO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1999
AB - New test structures for evaluating isolation capacitance (C_TS) and isolation breakdown voltage (BV_CCO) have been developed. Using these test structures, we examined the scaling limit of the width and the structure of narrow isolation U-grooves for high-speed and high-density LSIs. We separated the capacitance C_TS into two components, C_TSS (bottom component) and C_TSL (peripheral component), and analyzed the effect of the device structure (isolation width and filling materials) on C_TS. We found that the minimum width of the isolation U-groove is especially limited by the increased isolation capacitance between the neighboring N⁺ buried layers. The minimum width is about 0.3 µm even when SiO₂ is used as a filling material. So we developed an effective method to overcome this limitation. Use of a double-trench structure and/or an SOI substrate meet the requirement. A double-trench structure can reduce C_TS by more than 50%, while SOI substrates gives reduced C_TS, high BV_CCO, high α-ray immunity, and reduced process steps.
ER -