A compact new test structure using shift register circuits for extracting components of the capacitance matrix of the multi-layer interconnections has been proposed. An extraction method of the capacitance matrix is also presented. As a result of fabrication, capacitance values obtained by measurement are in good agreement with the numerical calculation. We also showed an estimation method of the measurement errors.

This paper reports on the use of microelectronic test structures to characterise a novel fabrication technique for thin-film electronic circuit boards. In this technology circuit tracks are formed on paper-like substrates by depositing films of a metal-loaded ink via a standard lithographic printing process. Sheet resistance and linewidth for both horizontal and vertical lines are electrically evaluated and these compared with optical and surface profiling measurements.

In this paper we present a complete methodology for efficient electro-mechanical characterization of a CMOS compatible MEMS technology. Using an original test structure, the so-called "U-shape cantilever beam," we are able to determine all mechanical characteristics of force sensors constituted with elementary beams in a given technology. A complete set of electro-mechanical relations for the design of Microsystems have also been developed.

A new method using new test structure, which is connected 15.4 million MOS transistor, for evaluating extrinsic oxide breakdown is proposed. The active gate area which is needed to predict reliability will be shown. And by using this new method, activation energy not only for the intrinsic breakdown but also for the extrinsic breakdown are obtained.

Profiles of photoemission induced by hot electrons in LDD-type n-MOSFETs with L = 0.35-2.0 µm were measured with a photoemission microscope, which had a capability of 1000 magnification and a spatial resolution of 27 nm/pixel on a CCD imager sufficient to detect profile changes in the channel length direction. Under the bias condition of maximum substrate current, photoemission peaks were located at the LDD-drain edge and the n⁺-drain edge for the devices with L = 0.35 and L 0.40 µm, respectively. A peak position, only in the case of the 0.35 µm device, shifted toward the drain side by about 80 nm at V_D = 7.0 V. Since V_D did not affect peak positions in L 0.40 µm devices, the photoemission mechanisms may be different between L = 0.35 µm and L 0.40 µm devices. The photoemission points due to p-n junction breakdown were located at the cylindrical curvature edge of the n⁺-drain region. Two-dimensional device simulation, even when the lateral electric field, electron temperature and radiative recombination rate were taken into account, could not explain the experimental results completely.

A new simple method for extracting the capacitance coupling coefficients of sub-0.5-µm flash memory cells is proposed. Different from the previously proposed methods, this method is not affected by a dopant profile of source region because a band-to-band tunneling current from the interface between the drain and the substrate is probed. Use of a reference device eliminates the necessity to make assumptions concerning the electron transport mechanism. Comparison with the other methods shows that the proposed method is simple and accurate.

A novel method of extraction of emitter, R_e, and base, R_b, resistances of bipolar junction transistors, BJTs, is proposed. R_e and R_b are obtained from static characteristics and noise power spectral density of low frequency, 1/f, fluctuations, measured in the base and collector currents of the devices. Measurements carried out on quasi self-aligned silicon BJTs show that R_e and R_b values obtained by the proposed method scale correctly with transistor dimensions and match the values estimated from the device layout.

New test structures for evaluating isolation capacitance (C_TS) and isolation breakdown voltage (BV_CCO) have been developed. Using these test structures, we examined the scaling limit of the width and the structure of narrow isolation U-grooves for high-speed and high-density LSIs. We separated the capacitance C_TS into two components, C_TSS (bottom component) and C_TSL (peripheral component), and analyzed the effect of the device structure (isolation width and filling materials) on C_TS. We found that the minimum width of the isolation U-groove is especially limited by the increased isolation capacitance between the neighboring N⁺ buried layers. The minimum width is about 0.3 µm even when SiO₂ is used as a filling material. So we developed an effective method to overcome this limitation. Use of a double-trench structure and/or an SOI substrate meet the requirement. A double-trench structure can reduce C_TS by more than 50%, while SOI substrates gives reduced C_TS, high BV_CCO, high α-ray immunity, and reduced process steps.

An advanced characterization method for sub-micron DRAM cell transistors has been proposed for the analysis of transistor test structures using memory cell patterns. When the actual memory cell layout is used as a test structure, the parasitic source and drain resistance of the test structure affected conventional transistor parameters such as threshold voltage. To solve this problem, reduced drain current measurement methods have been proposed to suppress the parasitic resistance voltage drop. In these measurements, two new transistor parameters, V_goff and V_gsat, have been proposed which are related to off-leakage and full writing, respectively. These parameters are found to be good parameters for monitoring DRAM bit failures. A new threshold voltage measurement methodology has also been proposed for test structures with high parasitic resistance.

In deep submicron CMOS and BICMOS technologies, antenna effects affect floating gate charge of usual floating gate test structures, dedicated to capacitor matching measurement. In this paper a new pseudo-floating gate test structure is designed. After test structure and modeling presentation, testing method and results are given for several capacitor layouts (poly-poly and metal-metal).

This paper presents a new technique for modeling High-Voltage lightly-doped-drain MOS (HV MOS) devices accurately with the BSIM3v3 SPICE model. Standard SPICE models do not model the voltage dependency of R_s and R_d in HV MOS devices; this causes large discrepancies between the simulated and measured I-V characteristics of HV MOS devices. We propose to assign physical meanings and values different from the original BSIM3v3 model to three of its parameters to represent the voltage dependency of R_s and R_d. With this method, we have succeeded in highly accurate parameter extraction, and the simulated I-V characteristics of HV MOS devices using the extracted parameters match the measured results well. The relationship between the proposed modeling technique and the physical mechanism of HV MOS devices is also discussed based on measurement and device simulation results. Since our method does not change any model equations of BSIM3v3, it can be applied to any SPICE simulator on which the BSIM3v3 model runs, so we can use SPICE simulation for accurate circuit design of complex circuits using HV MOS devices.

The effect of lot size change and test processing logistics on VLSI manufacturing final test process efficiency and cost due to the transition of from conventional 5 or 6 inches to 300 mm (12 inches) in wafer size is evaluated through simulation analysis. Simulated results show that a high test efficiency and a low test cost are maintained regardless of arrival lot size in the range of the number of 300 mm wafers per lot from 1 to 25 and the content of express lots in the range of up to 50% by using WEIGHT+RPM rule and the right final test processing logistics. WEIGHT+RPM rule is the rule that considers the jig and temperature exchanging time, the lot waiting time in queue and also the remaining processing time of the machine in use. The logistics has a small processing and moving lot size equal to the batch size of testing equipment.

We proposed Reversible Energy Recovery Logic (RERL) using an 8-phase clocking scheme, which is a dual-rail reversible adiabatic logic for ultra-low-energy applications. Because we eliminated non-adiabatic energy loss in RERL by using the concept of reversible logic, RERL has only adiabatic and leakage losses. In this paper we explain its operation and logic design and present its simulation and experimental results. We also present an energy-efficient 8-phase, clocked power generator that uses an off-chip inductor. With simulation results for the full adder, we confirmed that the RERL circuit consumed substantially less energy than other logic circuits at low-speed operation. We evaluated a test chip implemented with a 0.6-µm CMOS technology, which integrated a chain of inverters with a clocked power generator. In the experimental results, the RERL circuit consumed only 4.5% of the dissipated energy of a static CMOS circuit at an optimal operating speed of 40 kHz. In conclusion, RERL is suitable for the applications that do not require high performance but low-energy consumption because its energy consumption can be decreased to the minimum by reducing the operating frequency until adiabatic and leakage losses are equal.

We have investigated the operation of a reflection type magnetostatic wave signal-to-noise enhancer in detail. It has good enhancement characteristics, low insertion loss, and low operating power. It is also composed of a transducer using a ceramic substrate having a high dielectric constant and an LaGa-YIG film with low saturation magnetization to enable direct operation in the 400-MHz band (the IF band of current DBS receivers). Enhancement of 8 dB was achieved over a 40-MHz bandwidth. Although its operating frequency range depends critically on device temperature, we can compensate for the temperature dependence by adjusting the bias magnetic field. Experiments showed that the enhancer improved the received carrier-to-noise ratio by 2 to 3 dB, providing good noise reduction in DBS reception.

We first demonstrate a self-pulsation phenomenon in a semiconductor ring laser(SRL). Not only self-mode-locked optical pulse but self-Q-switched optical pulse can be observed in a SRL. Furthermore, experimental results show that the repetition period of the Q-switched optical pulse train can be controlled by the injection current to a SRL.

This paper presents a contact-less connector using proximity coupling through a parasitic element. For example, proximity coupling is used for interconnect of microstrip lines for DC-break structure. We also present a cross wiring structure using this interconnect.

A simple simulation approach based on the modified central difference (MCD) method for analyzing the coupling characteristics of coupled transmission lines (CTL) is presented. Gaussian pulse responses on the sense line are demonstrated by graphical expressions. The frequency characteristics of the coupling factor is efficiently derived from the extracted input and output responses by using the fast Fourier transform (FFT) technique. It is shown that this approach is useful to analyze the coupling characteristics of symmetrical and asymmetric multi-section CTL.