Profiles of photoemission induced by hot electrons in LDD-type n-MOSFETs with L = 0.35-2.0 µm were measured with a photoemission microscope, which had a capability of 1000 magnification and a spatial resolution of 27 nm/pixel on a CCD imager sufficient to detect profile changes in the channel length direction. Under the bias condition of maximum substrate current, photoemission peaks were located at the LDD-drain edge and the n+-drain edge for the devices with L = 0.35 and L 0.40 µm, respectively. A peak position, only in the case of the 0.35 µm device, shifted toward the drain side by about 80 nm at VD = 7.0 V. Since VD did not affect peak positions in L 0.40 µm devices, the photoemission mechanisms may be different between L = 0.35 µm and L 0.40 µm devices. The photoemission points due to p-n junction breakdown were located at the cylindrical curvature edge of the n+-drain region. Two-dimensional device simulation, even when the lateral electric field, electron temperature and radiative recombination rate were taken into account, could not explain the experimental results completely.

The electrical characteristics of sealed CMOSFETs with gates crossing sources/drains at 90 and 45 are experimentally investigated using test devices fabricated by an n-well CMOS process with trench isolation. Gain factors of surface-channel 90 and 45 n-MOSFETs can be estimated by a simple correction theory based on the combination of a center MOSFET and two edge MOSFETs. However, relatively large departures from the theory are observed in buried-channel 90 and 45 p-MOSFETs with widths less than the channel length. The difference between n- and p-MOSFETs is mainly due to the channel type. Other basic device parameters such as saturation drain currents, threshold voltages, subthreshold swings, maximum substrate currents and substrate-voltage dependence of threshold voltages are also measured and qualitatively explained.