A new test structure, which has a 0.5 µm line and space polysilicon pattern of which center is aligned on the MOSFET's gate center, is proposed for hot-carrier-induced photoemission analysis in subquarter micron devices. The photoemission-intensity profiles were measured using the photoemission microscope with a liquid N2 cooled CCD imager. We successfully measured a peak position of photoemission intensity from the center of MOSFET's gate with a spatial resolution sufficiently less than 24 nm at the microscope magnification of 1000. The test structure is useful to study the photoemission effects in semiconductor devices.

Profiles of photoemission induced by hot electrons in LDD-type n-MOSFETs with L = 0.35-2.0 µm were measured with a photoemission microscope, which had a capability of 1000 magnification and a spatial resolution of 27 nm/pixel on a CCD imager sufficient to detect profile changes in the channel length direction. Under the bias condition of maximum substrate current, photoemission peaks were located at the LDD-drain edge and the n+-drain edge for the devices with L = 0.35 and L 0.40 µm, respectively. A peak position, only in the case of the 0.35 µm device, shifted toward the drain side by about 80 nm at VD = 7.0 V. Since VD did not affect peak positions in L 0.40 µm devices, the photoemission mechanisms may be different between L = 0.35 µm and L 0.40 µm devices. The photoemission points due to p-n junction breakdown were located at the cylindrical curvature edge of the n+-drain region. Two-dimensional device simulation, even when the lateral electric field, electron temperature and radiative recombination rate were taken into account, could not explain the experimental results completely.