Hot-carrier degradation of voltage controlled oscillator (VCO) was investigated by a reliability simulator known as BERT. The appropriate monitor of VCO frequency degradation shifts from the saturated drain current of an N MOSFET to linear drain current with an increase in VCO input voltage. The degradation of the VCO drastically increases with a small reduction in initial oscillation frequency. These results imply the need for an appropriate reliability margin around the standard operating point as well as a performance margin, which cannot be achieved by using conventional drain current monitors.

A test structure and method for two-dimensional analysis of fabrication process variation of MOSFET using a photoemission microscope are presented. Arrays of 2010 (=200) MOSFETs were successfully measured at a time and evaluated the fluctuation of their characteristics. The fluctuation of hot-carrier-induced photoemission intensity was larger as gate length becomes smaller. Although the intensity fluctuation of photoemission in the same MOSFET was within small range, the fluctuation all over the MOSFET array was relatively large and independent of the position in the array. An estimation method of the gate length fluctuation has been demonstrated with the photoemission intensity distribution analysis.

A new test structure, which has a 0.5 µm line and space polysilicon pattern of which center is aligned on the MOSFET's gate center, is proposed for hot-carrier-induced photoemission analysis in subquarter micron devices. The photoemission-intensity profiles were measured using the photoemission microscope with a liquid N2 cooled CCD imager. We successfully measured a peak position of photoemission intensity from the center of MOSFET's gate with a spatial resolution sufficiently less than 24 nm at the microscope magnification of 1000. The test structure is useful to study the photoemission effects in semiconductor devices.

A simulation methodology to analyze hot-carrier degradation due to bidirectional stressing in a static RAM circuit has been developed. The bidirectional stressing of pass transistors can approximate to unidirectional stressing. The effective stress direction of each NMOSFET can be determined by the higher of the two junction voltages at the peak substrate current generation. Aged SPICE parameter sets extracted in the forward or in the reverse mode are selected for simulating the degradation of each NMOSFET. Furthermore, effects of each NMOSFET degradation on the degraded circuit behavior are simulated. This technique helps detect an NMOSFET having the largest influence on the circuit aging, improving circuit reliability. The methodology was successfully applied to an SRAM device, and was validated by low temperature bias test data.

A drain avalanche hot carrier lifetime model including a body effect caused by secondary hot electrons has been developed. It has been confirmed that the proposed model fits a wide range of experimental data using a small number of parameters. The model provides a practical modeling methodology for reliability simulation based on parameter extraction at maximum substrate current conditions alone. Simulation accuracy produced by the methodology has been experimentally verified using ring oscillators including NAND gates. It has been demonstrated that simulation accuracy of degradations has become by 0.34 decade better using the new methodology than using that based on the conventional τId/W-Isub/Id model.