A drain avalanche hot carrier lifetime model including a body effect caused by secondary hot electrons has been developed. It has been confirmed that the proposed model fits a wide range of experimental data using a small number of parameters. The model provides a practical modeling methodology for reliability simulation based on parameter extraction at maximum substrate current conditions alone. Simulation accuracy produced by the methodology has been experimentally verified using ring oscillators including NAND gates. It has been demonstrated that simulation accuracy of degradations has become by 0.34 decade better using the new methodology than using that based on the conventional τId/W-Isub/Id model.
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Norio KOIKE, Hirokazu YONEZAWA, "A Modeling Methodology and Body Effect Analysis for Hot-Carrier Reliability Simulation of Logic Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 6, pp. 1356-1366, June 2002, doi: .
Abstract: A drain avalanche hot carrier lifetime model including a body effect caused by secondary hot electrons has been developed. It has been confirmed that the proposed model fits a wide range of experimental data using a small number of parameters. The model provides a practical modeling methodology for reliability simulation based on parameter extraction at maximum substrate current conditions alone. Simulation accuracy produced by the methodology has been experimentally verified using ring oscillators including NAND gates. It has been demonstrated that simulation accuracy of degradations has become by 0.34 decade better using the new methodology than using that based on the conventional τId/W-Isub/Id model.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_6_1356/_p
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@ARTICLE{e85-c_6_1356,
author={Norio KOIKE, Hirokazu YONEZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Modeling Methodology and Body Effect Analysis for Hot-Carrier Reliability Simulation of Logic Circuits},
year={2002},
volume={E85-C},
number={6},
pages={1356-1366},
abstract={A drain avalanche hot carrier lifetime model including a body effect caused by secondary hot electrons has been developed. It has been confirmed that the proposed model fits a wide range of experimental data using a small number of parameters. The model provides a practical modeling methodology for reliability simulation based on parameter extraction at maximum substrate current conditions alone. Simulation accuracy produced by the methodology has been experimentally verified using ring oscillators including NAND gates. It has been demonstrated that simulation accuracy of degradations has become by 0.34 decade better using the new methodology than using that based on the conventional τId/W-Isub/Id model.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - A Modeling Methodology and Body Effect Analysis for Hot-Carrier Reliability Simulation of Logic Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1356
EP - 1366
AU - Norio KOIKE
AU - Hirokazu YONEZAWA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2002
AB - A drain avalanche hot carrier lifetime model including a body effect caused by secondary hot electrons has been developed. It has been confirmed that the proposed model fits a wide range of experimental data using a small number of parameters. The model provides a practical modeling methodology for reliability simulation based on parameter extraction at maximum substrate current conditions alone. Simulation accuracy produced by the methodology has been experimentally verified using ring oscillators including NAND gates. It has been demonstrated that simulation accuracy of degradations has become by 0.34 decade better using the new methodology than using that based on the conventional τId/W-Isub/Id model.
ER -