The search functionality is under construction.
The search functionality is under construction.

A Modeling Methodology and Body Effect Analysis for Hot-Carrier Reliability Simulation of Logic Circuits

Norio KOIKE, Hirokazu YONEZAWA

  • Full Text Views

    0

  • Cite this

Summary :

A drain avalanche hot carrier lifetime model including a body effect caused by secondary hot electrons has been developed. It has been confirmed that the proposed model fits a wide range of experimental data using a small number of parameters. The model provides a practical modeling methodology for reliability simulation based on parameter extraction at maximum substrate current conditions alone. Simulation accuracy produced by the methodology has been experimentally verified using ring oscillators including NAND gates. It has been demonstrated that simulation accuracy of degradations has become by 0.34 decade better using the new methodology than using that based on the conventional τId/W-Isub/Id model.

Publication
IEICE TRANSACTIONS on Electronics Vol.E85-C No.6 pp.1356-1366
Publication Date
2002/06/01
Publicized
Online ISSN
DOI
Type of Manuscript
PAPER
Category
Integrated Electronics

Authors

Keyword