A two-dimensional photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices with channel width ranging from 160 µm to 0.2 µm is described. Photoemission-intensity profiles can be measured in spatial resolution of 0.1 µm. Different photoemission characteristics are observed in n-MOSFETs depending on isolation technology; M-shaped photoemission-intensity profiles are observed as gate voltage becomes higher in trench-isolated ones, but scarcely measured in LOCOS-isolated ones. As for p-MOSFETs, similar characteristics are observed independent on isolation technology and slightly M-shaped profiles are observed at higher gate voltages. The recession of 0.1-0.2 µm in photoemission area from the gate electrode edge due to gate bias dependence of the pinch-off points of n--LDD drain is observed when gate voltage increases from 1 V to 6 V. Meanwhile the recession of the pinch-off points in p-MOSFETs is less than 0.1 µm even when gate voltage increases from 2 V to 8 V. A qualitative explanation for the experimental results is given for four kinds of MOSFETs in comparing each device structure near the isolation edge.

This paper describes the dynamic behavior of a trench capacitor dRAM cell, named the SCC (Surrounded high-Capacitor Cell). A transient three-dimensional simulation reveals the raising of the substrate potential and the leakage current in the low-to-high state operation. The simulation results are verified by the experimental data using a test device. The characterization of this phenomenon allows design consideration of the scaled SCC.

A new test structure, which has a 0.5 µm line and space polysilicon pattern of which center is aligned on the MOSFET's gate center, is proposed for hot-carrier-induced photoemission analysis in subquarter micron devices. The photoemission-intensity profiles were measured using the photoemission microscope with a liquid N2 cooled CCD imager. We successfully measured a peak position of photoemission intensity from the center of MOSFET's gate with a spatial resolution sufficiently less than 24 nm at the microscope magnification of 1000. The test structure is useful to study the photoemission effects in semiconductor devices.

A new design hierarchy in TCAD is discussed with emphasis on a design of IC interconnects and gate patterns. Two design methodologies for gate patterns at a CMOS cell level and multilevel interconnect scheme at a chip level are proposed. This approach generates the layout design rules of gate patterns, considering the fabrication process and pattern layout dependency, and allows a design of multilevel interconnect scheme at the initial phase of technology development.

This paper presents the dynamics of heavy-ion induced latchup turn-on behavior in CMOS structures using a three-dimensional and transient device simulation. The three-dimensional effects of parasitic devices in a CMOS structure during latchup turn-on are discussed in detail when a heavy-ion strikes the CMOS structure. For different incident types, the dynamics of latchup turn-on behaviors are also simulated. Moreover, latchup immunities of the CMOS structure obtained by two- and three-dimensional calculations are compared for the different incident types. This result suggests that the rough relation between latchup immunity and heavy-ion incident energy can be estimated using a two-dimensional simulation.