A Two-Dimensional Analysis of Hot-Carrier Photoemission from LOCOS- and Trench-Isolated MOSFETs

Takashi OHZONE; Hideyuki IWATA; Yukiharu URAOKA; Shinji ODANAKA

A Two-Dimensional Analysis of Hot-Carrier Photoemission from LOCOS- and Trench-Isolated MOSFETs

Takashi OHZONE, Hideyuki IWATA, Yukiharu URAOKA, Shinji ODANAKA

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A two-dimensional photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices with channel width ranging from 160 µm to 0.2 µm is described. Photoemission-intensity profiles can be measured in spatial resolution of 0.1 µm. Different photoemission characteristics are observed in n-MOSFETs depending on isolation technology; M-shaped photoemission-intensity profiles are observed as gate voltage becomes higher in trench-isolated ones, but scarcely measured in LOCOS-isolated ones. As for p-MOSFETs, similar characteristics are observed independent on isolation technology and slightly M-shaped profiles are observed at higher gate voltages. The recession of 0.1-0.2 µm in photoemission area from the gate electrode edge due to gate bias dependence of the pinch-off points of n^--LDD drain is observed when gate voltage increases from 1 V to 6 V. Meanwhile the recession of the pinch-off points in p-MOSFETs is less than 0.1 µm even when gate voltage increases from 2 V to 8 V. A qualitative explanation for the experimental results is given for four kinds of MOSFETs in comparing each device structure near the isolation edge.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.11 pp.1673-1682

Publication Date: 1993/11/25

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Takashi OHZONE, Hideyuki IWATA, Yukiharu URAOKA, Shinji ODANAKA, "A Two-Dimensional Analysis of Hot-Carrier Photoemission from LOCOS- and Trench-Isolated MOSFETs" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 11, pp. 1673-1682, November 1993, doi: .
Abstract: A two-dimensional photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices with channel width ranging from 160 µm to 0.2 µm is described. Photoemission-intensity profiles can be measured in spatial resolution of 0.1 µm. Different photoemission characteristics are observed in n-MOSFETs depending on isolation technology; M-shaped photoemission-intensity profiles are observed as gate voltage becomes higher in trench-isolated ones, but scarcely measured in LOCOS-isolated ones. As for p-MOSFETs, similar characteristics are observed independent on isolation technology and slightly M-shaped profiles are observed at higher gate voltages. The recession of 0.1-0.2 µm in photoemission area from the gate electrode edge due to gate bias dependence of the pinch-off points of n^--LDD drain is observed when gate voltage increases from 1 V to 6 V. Meanwhile the recession of the pinch-off points in p-MOSFETs is less than 0.1 µm even when gate voltage increases from 2 V to 8 V. A qualitative explanation for the experimental results is given for four kinds of MOSFETs in comparing each device structure near the isolation edge.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_11_1673/_p

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@ARTICLE{e76-c_11_1673,
author={Takashi OHZONE, Hideyuki IWATA, Yukiharu URAOKA, Shinji ODANAKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Two-Dimensional Analysis of Hot-Carrier Photoemission from LOCOS- and Trench-Isolated MOSFETs},
year={1993},
volume={E76-C},
number={11},
pages={1673-1682},
abstract={A two-dimensional photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices with channel width ranging from 160 µm to 0.2 µm is described. Photoemission-intensity profiles can be measured in spatial resolution of 0.1 µm. Different photoemission characteristics are observed in n-MOSFETs depending on isolation technology; M-shaped photoemission-intensity profiles are observed as gate voltage becomes higher in trench-isolated ones, but scarcely measured in LOCOS-isolated ones. As for p-MOSFETs, similar characteristics are observed independent on isolation technology and slightly M-shaped profiles are observed at higher gate voltages. The recession of 0.1-0.2 µm in photoemission area from the gate electrode edge due to gate bias dependence of the pinch-off points of n^--LDD drain is observed when gate voltage increases from 1 V to 6 V. Meanwhile the recession of the pinch-off points in p-MOSFETs is less than 0.1 µm even when gate voltage increases from 2 V to 8 V. A qualitative explanation for the experimental results is given for four kinds of MOSFETs in comparing each device structure near the isolation edge.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - A Two-Dimensional Analysis of Hot-Carrier Photoemission from LOCOS- and Trench-Isolated MOSFETs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1673
EP - 1682
AU - Takashi OHZONE
AU - Hideyuki IWATA
AU - Yukiharu URAOKA
AU - Shinji ODANAKA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1993
AB - A two-dimensional photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices with channel width ranging from 160 µm to 0.2 µm is described. Photoemission-intensity profiles can be measured in spatial resolution of 0.1 µm. Different photoemission characteristics are observed in n-MOSFETs depending on isolation technology; M-shaped photoemission-intensity profiles are observed as gate voltage becomes higher in trench-isolated ones, but scarcely measured in LOCOS-isolated ones. As for p-MOSFETs, similar characteristics are observed independent on isolation technology and slightly M-shaped profiles are observed at higher gate voltages. The recession of 0.1-0.2 µm in photoemission area from the gate electrode edge due to gate bias dependence of the pinch-off points of n^--LDD drain is observed when gate voltage increases from 1 V to 6 V. Meanwhile the recession of the pinch-off points in p-MOSFETs is less than 0.1 µm even when gate voltage increases from 2 V to 8 V. A qualitative explanation for the experimental results is given for four kinds of MOSFETs in comparing each device structure near the isolation edge.
ER -