MOS capacitors with Si-implanted thermal oxide and CVD deposited oxide of 30 nm thickness were fabricated for applications of non-volatile memory and electroluminescence devices. Current-voltage (I-V) and I-V hysteresis characteristics were measured, and the hysteresis window (HW) and the integrated charge of HW (ICHW) extracted from the hysteresis data were discussed. The HW characteristics of high Si dose samples showed the asymmetrical double-peaks curves with the hump in both tails. The ICHW almost converged after the 4th cycle and had the voltage sweep speed dependence. All +ICHW and -ICHW characteristics were closely related to the static (+I)-(+VG) and (-I)-(-VG) curves, respectively. For the high Si dose samples, the clear hump currents in the static I-VG characteristics contribute to lower the rising voltage and to steepen the ICHW increase, which correspond to the large stored charge in the oxide.

This paper presents the dynamics of heavy-ion induced latchup turn-on behavior in CMOS structures using a three-dimensional and transient device simulation. The three-dimensional effects of parasitic devices in a CMOS structure during latchup turn-on are discussed in detail when a heavy-ion strikes the CMOS structure. For different incident types, the dynamics of latchup turn-on behaviors are also simulated. Moreover, latchup immunities of the CMOS structure obtained by two- and three-dimensional calculations are compared for the different incident types. This result suggests that the rough relation between latchup immunity and heavy-ion incident energy can be estimated using a two-dimensional simulation.

In order to construct optical access networks economically for fiber to the home (FTTH), it is important to reduce the cost of optical fiber cable installation. Optical fiber and cable costs have been reduced over the past ten years, however there have been few reports describing installation cost reduction. In this paper, we describe the design of high-density optical fiber cable that reduces the required installation time. To achieve this we have reduced the optical fiber cable weight and the friction coefficient of the cable sheath. We reduced the cable weight by using polyethylene foam and a non-metallic tensile strength member made of a new material, PBO. These two approaches reduce the cable weight by a total of about 30%. We also added a lubricant to the polyethylene sheath of this cable and this reduced the pulling force required for the additional cable by 30%-50%.

A two-dimensional photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices with channel width ranging from 160 µm to 0.2 µm is described. Photoemission-intensity profiles can be measured in spatial resolution of 0.1 µm. Different photoemission characteristics are observed in n-MOSFETs depending on isolation technology; M-shaped photoemission-intensity profiles are observed as gate voltage becomes higher in trench-isolated ones, but scarcely measured in LOCOS-isolated ones. As for p-MOSFETs, similar characteristics are observed independent on isolation technology and slightly M-shaped profiles are observed at higher gate voltages. The recession of 0.1-0.2 µm in photoemission area from the gate electrode edge due to gate bias dependence of the pinch-off points of n--LDD drain is observed when gate voltage increases from 1 V to 6 V. Meanwhile the recession of the pinch-off points in p-MOSFETs is less than 0.1 µm even when gate voltage increases from 2 V to 8 V. A qualitative explanation for the experimental results is given for four kinds of MOSFETs in comparing each device structure near the isolation edge.

Electroluminescence (EL) under alternating-current (ac) operation is first reported for n+-polysilicon/SiO2/p-Si MOS capacitors with 50 nm Si-implanted SiO2. Visible EL can be observed with the naked eye in the dark. The ac operation by pulse-wave distinctly enhances the EL intensity and its lifetime. The pulse frequency affects the EL spectrum and thus the EL color. A model of EL mechanism is proposed for the Si-implanted MOS EL device, which has a possibility of visible light emitting device.

A test structure to analyze asymmetry and orientation dependence of MOSFETs is presented. n-MOSFETs with 8 different channel orientation and three kinds of process conditions were measured and symmetry characteristics of IDsat and IBmax with respect to the interchange of source and drain was examined. Although both IDsat and IBmax have similar channel orientation dependence, IBmax in interchanged S/D measurements shows asymmetrical characteristics, which can be applied to a sensitive method for device asymmetry detection.

A test structure and method for two-dimensional analysis of fabrication process variation of MOSFET using a photoemission microscope are presented. Arrays of 2010 (=200) MOSFETs were successfully measured at a time and evaluated the fluctuation of their characteristics. The fluctuation of hot-carrier-induced photoemission intensity was larger as gate length becomes smaller. Although the intensity fluctuation of photoemission in the same MOSFET was within small range, the fluctuation all over the MOSFET array was relatively large and independent of the position in the array. An estimation method of the gate length fluctuation has been demonstrated with the photoemission intensity distribution analysis.

A supply voltage (VDD) independent temperature sensor circuit, which can be realized by the optimum combination of three current modes of n-MOSFETs including the subthreshold current using the feedback scheme from the temperature dependent voltage (VTD) output to the gates of three n-MOSFETs, was proposed and fabricated by a standard 1.2 µm n-well CMOS process. The circuit consists of only 17 MOSFETs without high resistors resulting in a small die area of 0.18 mm2. The temperature coefficient TC of the sensor circuit can be controlled by the channel length ratio L4/L3 of two n-MOSFETs. The average temperature sensor voltage VTS and its typical TC are 1.77 V at VDD=5.0 V (20) and 5.1 mV/ for VDD=5.01.0 V in the temperature range of -20-100 in case of L4/L3=9, respectively.

The spread of optical access broadband networks using Fiber to the Home (FTTH) has not reached the rural areas of developing countries. The current state of global deployment of ICT indicates that it is difficult to sell network systems as stand-alone products due to prohibitive costs, and the demand is for total services that include construction, maintenance, and operation. Moreover, there is a need to offer proposals that include various solutions utilizing broadband networks, as well as for a business model that takes the sustainability of those solutions into consideration. In this paper, we discuss the issues in constructing broadband networks, introduce case studies of solutions using broadband networks for solving social issues in rural areas of developing countries, and discuss the challenges in the deployment of the solutions.

A test structure to separately measure sheet resistances of highly-doped-drain (HDD) and lightly-doped-drain (LDD) in LDD-type CMOSFETs with various gate spaces S having sub-100 nm sidewalls was proposed. From the reciprocal of source/drain-resistance R-1 versus S characteristics, the sheet resistance ρH of the high-conductive-region (HCR) corresponding to HDD and the approximate width WLC of the low-conductive-region (LCR) corresponding to LDD could be estimated. Both of ρH and WLC for p- and n-MOS devices were scarcely dependent on the gate voltage. The sidewall-width difference of 40 nm could be sufficiently detected by using the test structure with the S pitch of about 60 nm. The R-1 versus S characteristics showed the unstable resistance variations in the narrow S region less than 0.3 µm, which corresponded to the minimum S for the process used for the test device fabrication and suggested that various micro-loading effects seriously affected on the characteristics.

Heavy-ion-induced soft errors (single event upset) in submicron silicon-on-insulator (SOI) MOSFETs under space environmental conditions are studied over the temperature range of 100-400 K using three-dimensional device simulator with full-temperature models. The temperature dependence of the drain collected charge is examined in detail when a heavy-ion strikes the gate center perpendicularly. At very low temperatures, SOI MOSFETs have very high immunity to the heavy-ion-induced soft errors. In particular, alpha-particle-induced soft errors hardly occur at temperatures below 200 K. As the temperature increases, the collected charge shows a marked rate of increase. The problem of single event upset in SOI MOSFETs becomes more serious with increasing working temperature. This is because the induced bipolar mechanism is a main factor to cause charge collection in SOI MOSFETs and the bipolar current increases exponentially with increasing temperature. At room and high temperatures, the drain collected charge is strongly dependent on channel length and SOI film thickness.

A test structure to separately analyze the location where the hot-carrier-induced CMOSFET reliability is determined around the center or the isolation-edge along the channel-width was proposed and fabricated. The test structure has four kinds of MOSFETs; [A] and [D] MOSFETs with a short and a long channel-length all over the channel width, respectively, [B] MOSFET with the short and the long channel-length around the center and the both isolation-edges, respectively, and [C] MOSFET with the channel-length regions vice versa to the [B] MOSFET. The time dependent changes of the threshold voltages VT, the saturation currents IS, the linear currents IL and the maximum transconductances β up to 50,000 s were measured. All data for the wide channel-width MOSFETs were almost categorized into three; [A], [B]/[C] and [D]. The [B]/[C] data were well estimated from simple theoretical discussions by the combination of [A] and [D] data, which mean that the reliabilities are nearly the same around the center or the isolation-edge for the CMOSFETs.

The rapid spread of the Internet has led to the construction of broadband networks and the steady installation of optical fiber to the home. The air blowing cable system makes it possible to construct optical fiber networks efficiently and economically when the service demand is unpredictable. We have installed this system for intra-building applications. In this paper, we report ways of applying the air blowing system to aerial distribution using access networks. We showed that certain problems must be overcome before the system can be used for aerial applications. We describe these problems, which include those related to installation distance and environmental conditions and also the system components. In particular, the characteristics at high temperature were degraded because of a reduction in the flux. However, we were able to improve these characteristics by adopting the flexibility of the optical fiber unit.

High density and small diameter optical fiber cables are required in order to construct "Fiber To The Home (FTTH)" to support multi media services economically. By reducing the cable diameter and weight, it will be possible to install longer lengths of cable and use conduits more effectively. Moreover, the development of low loss multifiber connectors and joint boxes will reduce the joining time. It is expected that the achievement of the above will lead to reductions in installation and joining costs. This paper describes the design and performance of 1000-fiber single slotted core cable. Its diameter is 30 mm compared to 40 mm for currently used multi slotted core cable, and its weight is 0.85 kg/m compared to 1.4 kg/m. The reduced cable outer diameter and weight allow us to increase both the installed length from 1 to 2 km (pre-connectorized) and the maximum fiber count from 1000 to 1600 for multiple installation in a conduit. We also describe low loss 4, and 8 mechanically transferable (MT) connectors, a pulling head and a joint box. The average connection loss of those connectors is reduced from 0.35 to 0.2 dB. The cable joining time was greatly reduced from 9 to 4.5 hours by using 5 stacks of multi fiber connectors and newly developed pulling heads and a joint boxes. Finally, we describe field test results for 1000-fiber pre-connectorized cable. In field tests, this preconnectorized cable is sufficiently stable with present installation methods. These results will lead to reductions in installation and joining costs. The 1000-fiber pre-connectorized single slotted core cable is promising with regard to upgrading the access network towards FTTH.

A pure CMOS threshold-voltage reference (VTR) circuit achieves temperature (T) coefficient of 5 µV/(T = -60+100) and supply voltage (VDD) sensitivity of 0.1 mV/V (VDD = 35 V). A combination of subthreshold current, linear current and saturation current in n-MOSFETs provides a small voltage and temperature dependence. Three different regions in I-V characteristics of MOSFETs generate a constant VTR based on threshold voltage at 0 K. A feedback scheme from the reference output to gates of n-MOSFETs extremely stabilizes the output. The circuit consists of only 17 MOSFETs and its simple scheme saves the die area, which is 0.18 mm2 in the TEG (Test Element Group) chip fabricated by 1.2 µm n-well CMOS process.