The effects of fluorine implantation on flicker noise and reliability of NMOSFET and PMOSFETs were concurrently investigated. The flicker noise of an NMOSFET was decreased about 66% by fluorine implantation, and that of a PMOSET was decreased about 76%. As indicated by the results, fluorine implantation is one of the methods that can be used to improve the noise characteristics of MOSFET devices. However, hot-carrier degradation was enhanced by fluorine implantation in NMOSFETs, which can be related to the difference of molecular binding within the gate oxide. On the contrary, in case of PMOSFETs, NBTI life time was increased by fluorine implantation. Therefore, concurrent investigation of hot-carrier and NBTI reliability and flicker noise is necessary in developing MOSFETs for analog/digital mixed signal applications.

A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2 V.

A two-dimensional (2-D) physical model of n-channel poly-Si LDD TFTs in comparison with that of SD TFTs is presented to analyze hot-carrier degradation. The model is based on 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. We have shown that, in the current saturation bias (Vg

This paper presents an efficient application of hot-carrier reliability simulation to delay libraries of 0.18µm and 0.14µm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0-100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.

MOSFETs with sub-0.1 µm gate length were fabricated, and their low temperature operation was investigated. The drain current for drain voltage of 2 V increased monotonously as temperature was lowered to 15 K without an influence of the freeze-out effect. Moreover, the increase in the drain current was enhanced by the gate length reduction. The hot-carrier effect at low temperature was also investigated. Impact-ionization decreased as temperature was lowered under the condition of drain voltage 2 V. The decreasing ratio was enhanced as gate length became shorter. We consider this phenomenon is attributed to the non-steady-stationary effect. As a result, device degradation by DC stressing was reduced at 77 K in comparison with room temperature. In the case of 0.1 µm MOSFET, drain current was not degraded in condition of DC stress with gate- and drain-voltage was 1.5 V.

We have applied hot-carrier circuit-level simulation to memory peripheral circuits of a few thousand to over 12K transistors using a simple but accurate degradation model for reliability verification of actual memory products. By applying simulation to entire circuits, it was found that the location of maximum degradation depended greatly upon circuit configuration and device technology. A design curve has been developed to quickly relate device-level DC lifetime to circuit-level performance lifetime. Using these results in conjunction with a methodology that has been developed to predict hot-carrier degradation early in the design cycle before TEG fabrication, accurate total-circuit simulation is applied early in the design process, making reliability simulation a crucial design tool rather than a verification tool as technology advances into the deep sub-micron high clock rate regime.

The degradation of I-V characteristics under constant emitter-base reverse voltage stress in advanced self-aligned bipolar transistors was analyzed. Experimental analyses have been taken the stress field effect into account when predicting hot-carrier degradation. These analyses showed that base current starts to increase when the reverse voltage stress is about 3 V. The dependence of the base current change on reverse voltages of more than 3 V was also investigated experimentally, and equations expressing hot-carrier degradation in terms of the exponential dependence of excess base current on both reverse stress voltage and stress-enhancing voltage related to emitter-base breakdown voltage were derived.

Surface-channel PMOSFETs are suitable for use in the quarter micron CMOS devices. For surface-channel PMOSFETs with p+ poly-Si gates, boron penetration and hot-carrier effects were investigated. When the annealing temperature is higher and the gate oxide is thinner, a larger threshold voltage shift was observed for p+ poly-Si PMOSFETs, because of boron penetration. Furthermore, PMOSFETs with BF2-implanted gates cause larger boron penetration than those with Boron-implanted gates. Howerer, the PMOSFET lifetime, determined by hot-carrier reliability, does not depend on the degree of boron penetration. Instead, it depends on doping species, that is, BF2 and Boron. PMOSFETs with BF2-implanted gates have about 100 times longer lifetime than those with Boron-implanted gates. The main reason for the longer lifetime of BF2-doped PMOSFETs is the incorporation of fluorine in the gate oxide of the PMOSFET with the BF2-implanted gate, resulting in the smaller electron trapping in the gate oxide. The maximun allowed supply voltage,based on the hot-carrier reliability, is higher than4V for sub-half micron PMOSFETs with BF2- or Boron-implanted poly Si gates.

This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by 7% (50% compared to LDD FETs) due to suppressed gate-to-drain capacitance and improved lifetime by 10 times (300 times compared to LDD FETs). The buried-LATID FETs are very promising for deep-submicron MOSFETs to achieve improved performance and hot-carrier reliability at the same time.

Water desorption from interlayer dielectric, spin-on-glass and SiO2 film deposited with tetraethylorthosilicate and O3, was controlled in order to reduce MOSFET hot-carrier degradation by using plasma SiO2 film as a water blocking layer. Two kinds of plasma SiO2 film were used in this study: SiH4 plasma SiO2 film deposited with SiH4 and N2O, and TEOS plasma SiO2 film deposited with TEOS and O2. Thermal desorption spectroscopy was used to study water desorption. Reduction of water desorption was obtained using plasma SiO2 film with water blocking ability; this reduction of water desorption resulted in suppression of the MOSFET hot-carrier degradation. The water blocking ability was obtained by low pressure deposition for SiH4 plasma SiO2 and low flow rate ratio of TEOS to O2 deposition for TEOS plasma SiO2. Water absorption studies of plasma SiO2 film using Fourier transform infrared spectroscopy revealed that water blocking ability is associated with small amount of water absorption both in SiH4 plasma SiO2 film and in TEOS plasma SiO2 film. Consequently, it is considered that the water blocking ability, as well as water absorption, of plasma SiO2 film depends on porosity.

A two-dimensional photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices with channel width ranging from 160 µm to 0.2 µm is described. Photoemission-intensity profiles can be measured in spatial resolution of 0.1 µm. Different photoemission characteristics are observed in n-MOSFETs depending on isolation technology; M-shaped photoemission-intensity profiles are observed as gate voltage becomes higher in trench-isolated ones, but scarcely measured in LOCOS-isolated ones. As for p-MOSFETs, similar characteristics are observed independent on isolation technology and slightly M-shaped profiles are observed at higher gate voltages. The recession of 0.1-0.2 µm in photoemission area from the gate electrode edge due to gate bias dependence of the pinch-off points of n--LDD drain is observed when gate voltage increases from 1 V to 6 V. Meanwhile the recession of the pinch-off points in p-MOSFETs is less than 0.1 µm even when gate voltage increases from 2 V to 8 V. A qualitative explanation for the experimental results is given for four kinds of MOSFETs in comparing each device structure near the isolation edge.

A CMOS design to achieve high drivability is examined for lower power supply voltage in 0.5 µm ULSI. The design consists of two points. (1) A very narrow (50 nm) sidewall is used to achieve high drivability and also to obtain hot-carrier-reliability. (2) A retrograded channel profile with NMOS and PMOS is designed to achieve high drivability and also to reduce short channel effect. It is shown that the propagation delay times (tpd) of a unloaded Inverter and a loaded 2-way NAND gate are improved 30% with the newly designed CMOS, compared with the conventionally designed CMOS. It is also proved that the tpd keeps the scaling trend of the previous-5 V-era even in 3.3 V-era by adapting the newly designed CMOS. Moreover, 7.1 ns multiplication time of 1616-bit multiplier is obtained under 0.5 µm design rule.

A study of hot-carrier-induced photon emission in thin SOI/MOSFETs has been carried out both for bonded-SOI and SIMOX/SOI. The photon emission is observed not only in the drain region but also in the source region for SOI/MOSFETs, whereas only in the drain region for conventional bulk MOSFETs. From the emission spectrum, it can be concluded that the emission mechanism of the source region is probably a photon-assisted direct recombination of electrons and holes, while both the recombination and Bremsstrahlung are the possible mechanism for the drain region. The total photo intensity from SOI/MOSFETs increases as the SOI film thickness decreases, showing that strong impact ionization occurs near the drain region for thinner SOI devices. The relation between the lifetime and the photo intensity for SOI/MOSFETs is very similar to that between the lifetime and the substrate current for conventional bulk/MOSFETs, proving that photon emission is a good indicator of the hot carrier degradation in thin SOI/MOSFETs. The lifetime measurement using the photon emission both for SOI and bulk devices indicates that longer lifetime can be expected for thin film SOI/MOSFETs with a reduced drain bias which will be indispensable for future sub-half micron MOSFETs.

Hot-carrier characteristics in ultra-thin SOI MOSFET's (T-SOI MOSFET's) with gate-overlapped LDD have been investigated. The change in transistor static characteristics after hot carrier stress was mainly observed as positive threshold voltage (Vt) shifts due to trapped electrons, while in bulk-Si MOSFET's drain current degradation was dominant. The hot-carrier life time in T-SOI MOSFET's was comparable to that in bulk-Si devices at low drain voltage, but the life time dependence on drain voltage was different from that in bulk-Si MOSFET's, and the Vt degraded rapidly at the condition that parasitic bipolar breakdown began to occur. This implies that the drain supply voltage in T-SOI MOSFET's is determined directly by parasitic bipolar breakdown voltage unlike bulk-Si MOSFET's in which it is determined by hot-carrier reliability. The gate-overlapped LDD structure was compared with single drain structure and proved to provide better hot-carrier endurance by the improvement of the parasitic bipolar breakdown voltage. The hot-carrier reliability in the back channels of T-SOI MOSFET's was also investigated, and it was found that the back channel tends to be degraded more easily than front channel with large positive Vt shifts. These results suggest that the front Vt shifts in T-SOI devices are related with electron injection into the back surface of the T-SOI layer through charge coupling at the condition that the parasitic bipolar breakdown occurs.