We have demonstrated high mobility MOS transistors on high quality epitaxial SiGe films selectively grown on Si (100) substrates. The hole mobility enhancement afforded intrinsically by the SiGe channel (60%) is further increased by an optimized Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. Surface orientation, channel direction, and uniaxial strain technologies for SiGe channels CMOS further enhance transistor performances. On a (110) surface, the hole mobility of SiGe pMOS is greater on a (110) surface than on a (100) surface. Both electron and hole mobility on SiGe (110) surfaces are further enhanced in a <110> channel direction with appropriate uniaxial channel strain. We finally address low drive current issue of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. Results are supported by interface trap density (Dit) and specific contact resistivity (ρc).

In this paper, we suggest a novel pnp BJT structure to improve the matching characteristics of the bipolar junction transistor (BJT) which is fabricated using standard CMOS process. In the case of electrical characteristics, the collector current density Jc of the proposed structure (T2) is a little greater than the conventional structure (T1), which contributes to the greater current gain β of the proposed structure than the conventional structure. Although the matching characteristics of the collector current density of the proposed structure is almost similar to the conventional structure, that of the current gain of the proposed structure is better than the conventional structure about 14.81% due to the better matching characteristics of the base current density of the proposed structure about 59.34%. Therefore, the proposed BJT structure is desirable for high performance analog/digital mixed signal application.

A novel NiSi technology with bi-layer Co/TiN structure as a capping layer is proposed for the highly thermal immune Ni Silicide technology. Much better thermal immunity of Ni Silicide was certified up to 700, 30 min post silicidation furnace annealing by introducing Co/TiN bi-layer capping. The proposed structure is successfully applied to nano-scale CMOSFET with a gate length of 80 nm. The sheet resistance of nano-scale gate poly shows little degradation even after the high temperature furnace annealing of 650, 30 min. The Ni/Co/TiN structure is very promising for the nano-scale MOSFET technology which needs the ultra shallow junction and high temperature post silicidation processes

The effects of fluorine implantation on flicker noise and reliability of NMOSFET and PMOSFETs were concurrently investigated. The flicker noise of an NMOSFET was decreased about 66% by fluorine implantation, and that of a PMOSET was decreased about 76%. As indicated by the results, fluorine implantation is one of the methods that can be used to improve the noise characteristics of MOSFET devices. However, hot-carrier degradation was enhanced by fluorine implantation in NMOSFETs, which can be related to the difference of molecular binding within the gate oxide. On the contrary, in case of PMOSFETs, NBTI life time was increased by fluorine implantation. Therefore, concurrent investigation of hot-carrier and NBTI reliability and flicker noise is necessary in developing MOSFETs for analog/digital mixed signal applications.

In this paper, we fabricated a gate-all-around bandgap-engineered (BE) silicon-oxide-nitride-oxide-silicon (SONOS) and silicon-oxide-high-k-oxide-silicon (SOHOS) flash memory device with a vertical silicon pillar type structure for a potential solution to scaling down. Silicon nitride (Si3N4) and hafnium oxide (HfO2) were used as trapping layers in the SONOS and SOHOS devices, respectively. The BE-SOHOS device has better electrical characteristics such as a lower threshold voltage (VTH) of 0.16 V, a higher gm.max of 0.593 µA/V and on/off current ratio of 5.76108, than the BE-SONOS device. The memory characteristics of the BE-SONOS device, such as program/erase speed (P/E speed), endurance, and data retention, were compared with those of the BE-SOHOS device. The measured data show that the BE-SONOS device has good memory characteristics, such as program speed and data retention. Compared with the BE-SONOS device, the erase speed is enhanced about five times in BE-SOHOS, while the program speed and data retention characteristic are slightly worse, which can be explained via the many interface traps between the trapping layer and the tunneling oxide.