LATID (Large-Angle-Tilt Implanted Drain) FETs with Buried n- Profile for Deep-Submicron ULSIs
Summary :
This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.3 pp.350-354
- Publication Date
- 1994/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
- Category
- Device Technology
Authors
Keyword
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Junji HIRASE, Takashi HORI, Yoshinori ODAKE, "LATID (Large-Angle-Tilt Implanted Drain) FETs with Buried n- Profile for Deep-Submicron ULSIs" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 3, pp. 350-354, March 1994, doi: .
Abstract: This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_3_350/_p
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@ARTICLE{e77-c_3_350,
author={Junji HIRASE, Takashi HORI, Yoshinori ODAKE, },
journal={IEICE TRANSACTIONS on Electronics},
title={LATID (Large-Angle-Tilt Implanted Drain) FETs with Buried n- Profile for Deep-Submicron ULSIs},
year={1994},
volume={E77-C},
number={3},
pages={350-354},
abstract={This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - LATID (Large-Angle-Tilt Implanted Drain) FETs with Buried n- Profile for Deep-Submicron ULSIs
T2 - IEICE TRANSACTIONS on Electronics
SP - 350
EP - 354
AU - Junji HIRASE
AU - Takashi HORI
AU - Yoshinori ODAKE
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1994
AB - This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by
ER -
English
