SiC-MOSFETs are being increasingly implemented in power electronics systems as low-loss, fast switching devices. Despite the advantages of an SiC-MOSFET, its large dv/dt or di/dt has fear of electromagnetic interference (EMI) noise. This paper proposes and demonstrates a simple and robust gate driver that can suppress ringing oscillation and surge voltage induced by the turn-off of the SiC-MOSFET body diode. The proposed gate driver utilizes the channel leakage current methodology (CLC) to enhance the damping effect by elevating the gate-source voltage (VGS) and inducing the channel leakage current in the device. The gate driver can self-adjust the timing of initiating CLC operation, which avoids an increase in switching loss. Additionally, the output voltage of the VGS elevation circuit does not need to be actively controlled in accordance with the operating conditions. Thus, the circuit topology is simple, and ringing oscillation can be easily attenuated with fixed circuit parameters regardless of operating conditions, minimizing the increase in switching loss. The effectiveness and versatility of proposed gate driver were experimentally validated for a wide range of operating conditions by double and single pulse switching tests.

In response to fast charging systems, Silicon Carbide (SiC) power semiconductor devices are of great interest of the automotive power electronics applications as the next generation of fast charging systems require high voltage batteries. For high voltage battery EVs (Electric Vehicles) over 800V, SiC power semiconductor devices are suitable for 3-phase inverters, battery chargers, and isolated DC-DC converters due to their high voltage rating and high efficiency performance. However, SiC-MOSFETs have two characteristics that interfere with high-speed switching and high efficiency performance operations for SiC MOS-FET applications in automotive power electronics systems. One characteristic is the low voltage rating of the gate-source terminal, and the other is the large internal gate-resistance of SiC MOS-FET. The purpose of this work was to evaluate a proposed hybrid gate drive circuit that could ignore the internal gate-resistance and maintain the gate-source terminal stability of the SiC-MOSFET applications. It has been found that the proposed hybrid gate drive circuit can achieve faster and lower loss switching performance than conventional gate drive circuits by using the current source gate drive characteristics. In addition, the proposed gate drive circuit can use the voltage source gate drive characteristics to protect the gate-source terminals despite the low voltage rating of the SiC MOS-FET gate-source terminals.

A temperature-variation-tolerant intermittent startup circuit (ISC) that suppresses quiescent current to 300nA at 0.48V was developed. The ISC is a key circuit for a batteryless wireless sensor that can detect a 1μA generation current of energy harvesting sources from the intervals of wireless signals. The ISC consists of an ultralow-voltage detector composed of a depletion-type MOSFET and low-Vth MOSFETs, a Dickson-type gate-boosted charge pump circuit, and a power-switch control circuit. The detector consists of a voltage reference comparator and a feedback-controlled latch circuit for a hysteresis function. The voltage reference comparator, which has a common source stage with a folded constant-current-source load composed of a depletion-type nMOSFET, makes it possible to reduce the temperature dependency of the detection voltage, while suppressing the quiescent current to 300nA at 0.48V. The ISC fabricated with fully-depleted silicon-on-insulator (FD-SOI) CMOS technology also suppresses the variation of the quiescent current. To verify the effectiveness of the circuit, the ISC was fabricated in a 0.8-μm triple-Vth FD-SOI CMOS process. An experiment on the fabricated system, the ISC boosts the input voltage of 0.48V to 2.4V while suppressing the quiescent current to less than 300nA at 0.48V. The measured temperature coefficient of the detection voltage was ±50ppm/°C. The fluctuation of the quiescent current was 250nA ± 90nA in the temperature range from 0°C to 40°C. An intermittent energy harvesting sensor with the ISC was also fabricated. The sensor could detect a generation current of 1μA at EH sources within an accuracy of ±15% in the temperature range from 0°C to 40°C. It was also successfully applied to a self-powered wireless plant-monitoring sensor system.

In this study, the transient characteristics on the super-steep subthreshold slope (SS) of a PN-body tied (PNBT) silicon-on-insulator field-effect transistor (SOI-FET) were investigated using technology computer-aided design and pulse measurements. Carrier charging effects were observed on the super-steep SS PNBT SOI-FET. It was found that the turn-on delay time decreased to nearly zero when the gate overdrive-voltage was set to 0.1-0.15 V. Additionally, optimizing the gate width improved the turn-on delay. This has positive implications for the low speed problems of this device. However, long-term leakage current flows on turn-off. The carrier lifetime affects the leakage current, and the device parameters must be optimized to realize both a high on/off ratio and high-speed operation.

The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.

With the advantages of higher blocking voltage, higher operation temperature, fast-switching characteristics, and lower switching losses, the silicon carbide (SiC) MOSFET has attracted more attentions and become an available replacement of traditional silicon (Si) power semiconductor in applications. Despite of all the merits above, electromagnetic interference (EMI) issues will be induced consequently by the ultra-fast switching transitions of the SiC MOSFET. To quickly and precisely assess the switching behaviors of the SiC MOSFET for EMI investigation, an analytical model is proposed. This model has comprehensively considered most of the key factors, including parasitic inductances, non-linearity of the junction capacitors, negative feedback effect of Ls and Cgd shared by the power and the gate stage loops, non-linearity of the trans-conductance, and skin effect during voltage and current ringing stages, which will considerably affect the switching performance of the SiC MOSFET. Additionally, a finite-state machine (FSM) is especially utilized so as to analytically and intuitively describe the switching behaviors of the SiC MOSFET via Stateflow. Based on double pulse test (DPT), the effectiveness and correctness of the proposed model are validated through the comparison between the calculated and the measured waveforms during switching transitions. Besides, the model can appropriately depict the spectrum of the drain-source voltage of the MOSFET and is suitable for EMI investigation in applying of SiC devices.

This report focuses on an optimization scheme of advanced MOSFETs for designing CMOS circuits with high power efficiency. For this purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift relative to long-channel MOSFETs, provides a consistent measure for device-performance degradation with reduced channel length. However, performance degradations of CMOS circuits such as the power loss cannot be predicted by the threshold-voltage shift alone. Here, the subthreshold swing is identified as an additional important measure for power-efficient CMOS circuit design. The increase of the subthreshold swing is verified to become obvious when the threshold-voltage shift is larger than 0.15V.

In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).

Circuit performance of SiC-MOSFET-based bidirectional isolated DC/DC converters is investigated based on circuit simulation with the physically accurate compact device model HiSIM_HV. It is demonstrated that the combined optimization of the MOSFETs Ron and of the inductances in the transformer can enable a conversion efficiency of more than 97%. The simulation study also verifies that the possible efficiency improvements are diminished due to the MOSFET-performance degradation, namely the carrier-mobility reduction, which results in a limitation of the possible Ron reduction. It is further demonstrated that an optimization of the MOSFET-operation conditions is important to utilize the resulting higher MOSFET performance for achieving additional converter efficiency improvements.

An application of laser annealing process, which is used to form the P-type Base junction for high-performance low-voltage power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), is proposed. An equivalent shallow-junction structure for P-Base junction with uniform impurity distribution is achieved by adopting green laser annealing of pulsed mode. Higher impurity activation for the shallow junction has been achieved by the laser annealing of melted phase than by conventional RTA (Rapid Thermal Annealing) of solid phase. The application of the laser annealing technology in the fabrication process of Low-Voltage U-MOSFET is also examined.

An application of laser annealing process, which is used to form the shallow P-type Base junction for 20-V planar power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) is proposed. We demonstrated that the fabricated devices integrated with laser annealing process have superior electrical characteristics than those fabricated according to the standard process. Moreover, the threshold voltage variation of the devices applied by the new annealing process is effectively suppressed. This is due to that a uniform impurity distribution at the channel region is achieved by adopting laser annealing. Laser annealing technology can be applied as a reliable, effective, and advantageous process for the low-voltage power MOSFETs.

The threshold voltage variations for actual size MOSFETs obtained by capacitance measurement are compared with those obtained by the current measurement, and their differences are studied for the first time. It is found that the threshold voltage variations obtained by the capacitance measurement show the similar behavior to those current measurement and the absolute value is less than those obtained by the current measurement. The reason for the difference is partially explained by that the local channel dopant non-uniformity along the current path makes the threshold voltage variation obtained from current measurement larger. It is found that the flat-band voltage variations, which are obtained from the measured C-V curves, are small and not significant to the threshold voltage variation.

In this paper, an analytical threshold voltage model of the strained gate-all-around MOSFET fabricated on the Si1-xGex virtual substrate is presented by solving the two-dimensional Poisson equation. The impact of key parameters such as the strain, channel length, gate oxide thickness and radius of the silicon cylinder on the threshold voltage has been investigated. It has been demonstrated that the threshold voltage decreases as the strain in the channel increases. The threshold voltage roll-off becomes severe when increasing the Ge content in the Si1-xGex virtual substrate. The model is found to tally well with the device simulator.

The short-channel effect (SCE) in a MOSFET with an atomically thin MoS$_{2}$ channel was studied using a TCAD simulator. We derived the surface potential roll-up, drain-induced barrier lowering (DIBL), threshold voltage, and subthreshold swing (SS) as indexes of the SCE and analyzed their dependency on the channel thickness (number of atomic layers) and channel length. The minimum scalable channel length for a one-atomic-layer-thick MoS$_{2}$ MOSFET was determined from the threshold voltage roll-off to be 7.6,nm. The one-layer-thick device showed a small DIBL of 87,mV/V at a 20 nm gate length. By using high-k gate insulator, an SS lower than 70,mV/dec is achievable in sub-10-nm-scale devices.

A test structure for charge-based capacitance measurement (CBCM) method has been developed to evaluate the threshold voltage variability from capacitance-voltage (C-V) curves of actual size metal-oxide-semiconductor field-effect-transistors (MOSFETs). The C-V curves from accumulation to inversion are measured for the MOSFETs having various channel dimensions using this test structure. Intrinsic capacitance components between the MOSFET electrodes are extracted from those C-V curves which are considered to include parasitic capacitance component. The intrinsic C-V curves are used for attempting to extract threshold voltage variations of their MOSFETs. It is found that the developed test structure is very useful for the evaluation of MOSFETs variability, because the derivation in MOSFET C-V curves is not influenced by current measurement noise.

A low VDD current mirror with deep sub-micron vertical MOSFETs is presented. The keys are new bias circuits to reduce both the minimum VDD for the operation and the sensitivity of the output current on VDD. In the simulation, our circuits reduce the minimum VDD by about 17% and the VDD sensitivity by one order both from those of the conventional. In the simulation with 90nm φ vertical MOSFET approximate models, our circuit shows about 4MΩ output resistance at 1.2-V VDD with the small temperature dependence, which is about six times as large as that with planar MOSFETs.

The delay time component (τs) of an InGaAs MOSFET caused by dynamic source resistance is discussed. On the basis of the relationship between the current density (J) and the dynamic source resistance (rs), the value of rs is proportional to 1/J with some offset at low current densities, whereas the offset becomes smaller in a region of high current density. The value of τs depends on the current in a way similar to rs. Because the offset in the high-current-density region is proportional to the square root of the effective mass, an InGaAs MOSFET with a small mass has a shorter rs than a Si MOSFET.

Voltage multiplier (VM) circuits for RF (2.45GHz)-to-DC conversion are developed for battery-less sensor nodes. Converted DC power is charged on a storage capacitor before driving a wireless sensor module. A charging time of the storage capacitor of the proposed VM circuits is reduced 1/10 of the conventional VM circuits, because they have constant current characteristics owing to self-control of body bias in diode-connected SOI MOSFETs. The wireless sensor system composed of the fabricated VM chip and a commercially available sensor module is operated using an RF signal of a wireless LAN modem (2.45GHz) as a power source.

The linearity analysis of a passive mixer is presented. The distortion mechanism caused by switching operation of a MOS transistor is elucidated from the static and dynamic analysis of passive mixers. Furthermore, the maximum input and output level to keep linear operation and its required bias conditions are expressed by simple equations. The maximum linear output amplitude of the passive mixer is determined only by the local signal amplitude and it does not depend on input and output impedance. The calculated linearity performances agree well with simulated and measured results.

The self-improvement of static random access memory (SRAM) cell stability by post-fabrication high-voltage stress is experimentally demonstrated and its mechanism is analyzed using 4k device-matrix-array (DMA) SRAM test element group (TEG). It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to the VDD terminal of SRAM. It is newly found that | VTH| of the OFF-state pFETs in the SRAM cell is selectively lowered which improves the cell stability and contributes to the self-improvement.