IEICE TRANSACTIONS on Electronics
Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications
Summary :
In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E101-C No.3 pp.143-150
- Publication Date
- 2018/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E101.C.143
- Type of Manuscript
- PAPER
- Category
- Electromagnetic Theory
Authors
Shen-Li CHEN
National United University
Yu-Ting HUANG
Powerchip Technology Corporation
Shawn CHANG
Maxchip Technology Corporation
Keyword
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Shen-Li CHEN, Yu-Ting HUANG, Shawn CHANG, "Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications" in IEICE TRANSACTIONS on Electronics,
vol. E101-C, no. 3, pp. 143-150, March 2018, doi: 10.1587/transele.E101.C.143.
Abstract: In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E101.C.143/_p
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@ARTICLE{e101-c_3_143,
author={Shen-Li CHEN, Yu-Ting HUANG, Shawn CHANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications},
year={2018},
volume={E101-C},
number={3},
pages={143-150},
abstract={In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).},
keywords={},
doi={10.1587/transele.E101.C.143},
ISSN={1745-1353},
month={March},}
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TY - JOUR
TI - Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 143
EP - 150
AU - Shen-Li CHEN
AU - Yu-Ting HUANG
AU - Shawn CHANG
PY - 2018
DO - 10.1587/transele.E101.C.143
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E101-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2018
AB - In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).
ER -
English
