In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (I_t2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas I_t2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (V_h) decreased by approximately 5.45% for the LV nMOS-SJ, whereas V_h increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) I_t2 and V_h, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).

We present a design approach and analysis of a multimode stripline resonator (MSR). Furthermore, a bandpass filter (BPF) using a single MSR is presented. MSR has three fundamental modes, incorporating two transmission resonance modes and one quasi-lumped component (LC) resonance mode. The resonant frequencies and unloaded Q factors of those modes are theoretically derived by transmission modes and LC modes. By our equations, it is also explained that the resonant frequencies can be shown to be easily handled by an increase and decrease in the number of via holes. These frequencies calculated by our equations are in good agreement with those of 3-D simulations and measurements. Finally, design approach of a narrow bandpass filter using our resonator is introduced. Good agreement between measured and computed result is obtained.

This paper presents a fully integrated 32-MHz relaxation oscillator (ROSC) capable of sub-1-µs start-up time operation for low-power intermittent VLSI systems. The proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-µm CMOS demonstrated that the ROSC generates a stable clock frequency of 32.6 MHz within 1-µs start-up time. Measured line regulation and temperature coefficient were ±0.69% and ±0.38%, respectively.

A memory controller refreshes DRAM rows periodically in order to prevent DRAM cells from losing data over time. Refreshes consume a large amount of energy, and the problem becomes worse with the future larger DRAM capacity. Previously proposed selective refreshing techniques are either conservative in exploiting the opportunity or expensive in terms of required implementation overhead. In this paper, we propose a novel DRAM selective refresh technique by using page residence in a memory hierarchy of hardware-managed TLB. Our technique maximizes the opportunity to optimize refreshing by activating/deactivating refreshes for DRAM pages when their PTEs are inserted to/evicted from TLB or data caches, while the implementation cost is minimized by slightly extending the existing infrastructure. Our experiment shows that the proposed technique can reduce DRAM refresh power 43.6% on average and EDP 3.5% with small amount of hardware overhead.

Phase locking with frequency tuning is demonstrated for a resonant-tunneling-diode terahertz oscillator integrated with a biased varactor diode. The tuning range of oscillation frequency is 606-613GHz. The phase noise in the output of the oscillator is transformed to amplitude noise, and fed back to the varactor diode together with bias voltage. The spectral linewidth at least <2Hz was obtained at the oscillation frequencies tuned by the bias voltage of the varactor diode.