A delay-compensation circuit for low-power subthreshold digital circuits is proposed. Delay in digital circuits operating in the subthreshold region of MOSFETs changes exponentially with process and temperature variations. Threshold-voltage monitoring and supply-voltage scaling techniques are adopted to mitigate such variations. The variation in the delay can be significantly reduced by monitoring the threshold voltage of a MOSFET in each LSI chip and exploiting the voltage as the supply voltage for subthreshold digital circuits. The supply voltage generated by the threshold voltage monitoring circuit can be regarded as the minimum supply voltage to meet the delay constraint. Monte Carlo SPICE simulations demonstrated that a delay-time variation can be improved from having a log-normal to having a normal distribution. A prototype in a 0.35-µm standard CMOS process showed that the exponential delay variation with temperature of the ring-oscillator frequency in the range from 0.321 to 212 kHz can remain by using compensation in the range from 5.26 to 19.2 kHz.

We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.

In an LSI design process, Engineering Change Orders (ECO's) are often given even after the layout process. This letter presents an approach to change the design to satisfy the new specification with ECO's by employing an error diagnosis technique. Our approach performs incremental synthesis using spare cells embedded on the original layout. Experimental results show that applying the error diagnosis technique to incremental synthesis is effective to suppress increase in delay time caused by ECO's.

In this paper, we propose an error diagnosis technique based on clustering LUT elements to shorten the processing time. By grouping some elements as a cluster, our technique reduces the number of elements to be considered, which is effective to shorten the processing time for screening error location sets. First, the proposed technique partitions the circuit into FFR (fanout-free region) called cluster, which is a subcircuit composed of LUT elements without fanout. After screening the set of clusters including error locations, this technique screens error location sets composed of elements in the remaining set of clusters, where corrections should be made. Experimental results with benchmark circuits have shown that our technique shortens the processing time to 1/170 in the best case, and rectifies circuits including 6 errors which cannot be rectified by the conventional technique.

This paper proposes image super-resolution techniques with multi-channel convolutional neural networks. In the proposed method, output pixels are classified into K×K groups depending on their coordinates. Those groups are generated from separate channels of a convolutional neural network (CNN). Finally, they are synthesized into a K×K magnified image. This architecture can enlarge images directly without bicubic interpolation. Experimental results of 2×2, 3×3, and 4×4 magnifications have shown that the average PSNR for the proposed method is about 0.2dB higher than that for the conventional SRCNN.

This paper proposes multi-gate reconfigurable (RECON) cells and a technology remapping approach using them as spare cells for post-mask functional engineering change orders (ECOs). With the rapid increase in circuit complexity, ECOs often occur in the post-mask stage of LSI designs. To deal with post-mask ECOs at a low cost, only the metal layers are redesigned by making functional changes using spare cells. For this purpose, 2T/4T/6T-RECON cells were proposed as reconfigurable spare cells. However, conventional RECON cells are used to implement single functions, which may result in unused transistors in the cells. In addition, the number of 2T/4T/6T-RECON spare cells used for post-mask ECOs varies greatly depending on the circuit to be implemented and the type of ECO that occurs. Therefore, functional ECOs may fail due to a lack of certain types of RECON cells, even if other types of RECON cells remain. To solve this problem, we propose multi-gate RECON cells that implement multiple functions in a single RECON cell while retaining the layouts of conventional 4T/6T-RECON base cells, and a technology remapping approach using them. The proposed approach not only reduces the number of used spare cells for modifications but also allows the flexible use of spare cells to fix them with less increase in wire length and delay. Experimental results have confirmed that the functional ECO success ratio is increased by 4.8pt on average and the total number of used spare cells is reduced by 5.6% on average. It has also been confirmed that the increase in wire length is reduced by 17.4% on average and the decrease in slack is suppressed by 21.6% on average.

This paper presents a fully integrated voltage boost converter consisting of a charge pump (CP) and maximum power point tracking (MPPT) controller for ultra-low power energy harvesting. The converter is based on a conventional CP circuit and can deliver a wide range of load current by using nMOS and pMOS driver circuits for highly efficient charge transfer operation. The MPPT controller we propose dissipates nano-watt power to extract maximum power regardless of the harvester's power generation conditions and load current. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73% power conversion efficiency when the output power was 348µW. The circuit can operate at an extremely low input voltage of 0.21V.

A fully on-chip CMOS relaxation oscillator (ROSC) with a PVT variation compensation circuit is proposed in this paper. The circuit is based on a conventional ROSC and has a distinctive feature in the compensation circuit that compensates for comparator's non-idealities caused by not only offset voltage, but also delay time. Measurement results demonstrated that the circuit can generate a stable clock frequency of 6.66kHz. The current dissipation was 320nA at 1.0-V power supply. The measured line regulation and temperature coefficient were 0.98%/V and 56ppm/°C, respectively.

This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The proposed ROSC employs a compensation circuit of a comparator's non-idealities caused by offset voltage and delay time. The ROSC can generate a stable, and 32-kHz oscillation clock frequency without increasing power dissipation by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-$mu$m CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55,kHz with low power dissipation of 472,nW at 1.8-V power supply. Measured line regulation and temperature coefficient were 1.1%/V and 120,ppm/$^{circ}$C, respectively.

In this paper, we propose a low-power circuit-shared static flip-flop (CS2FF) for extremely low power digital VLSIs. The CS2FF consists of five static NORs and two inverters (INVs). The CS2FF utilizes a positive edge of a buffered clock signal, which is generated from a root clock, to take data into a master latch and a negative edge of the root clock to hold the data in a slave latch. The total number of transistors is only 24, which is the same as the conventional transmission-gate flip flop (TGFF) used in the most standard cell libraries. SPICE simulations in 0.18-µm standard CMOS process demonstrated that our proposed CS2FF achieved clock-to-Q delay of 18.3ns, setup time of 10.0ns, hold time of 5.5ns, and power dissipation of 9.7nW at 1-MHz clock frequency and 0.5-V power supply. The physical design area increased by 16% and power dissipation was reduced by 13% compared with those of conventional TGFF. Measurement results demonstrated that our proposed CS2FF can operate at 0.352V with extremely low energy of 5.93fJ.

Convolutional neural network (CNN)-based image super-resolutions are widely used as a high-quality image-enhancement technique. However, in general, they show little to no luminance isotropy. Thus, we propose two methods, “Luminance Inversion Training (LIT)” and “Luminance Inversion Averaging (LIA),” to improve the luminance isotropy of CNN-based image super-resolutions. Experimental results of 2× image magnification show that the average peak signal-to-noise ratio (PSNR) using Luminance Inversion Averaging is about 0.15-0.20dB higher than that for the conventional super-resolution.

Instability of SRAM memory cells derived from aggressive technology scaling has been recently one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. In order to assist the write operation, we address a new memory cell employing a look-ahead body-bias which dynamically controls the threshold voltage. Simulation results have shown improvement in both the write margins and access time without increasing the leakage power derived from the body-bias.

A triple density Error Diffusion for medical monochrome LCDs is proposed to improve their gray-scale precisions. In addition, a measurement technique of image qualities based on E-MSE (Eye model-based Mean Square Error) is proposed. Several conventional techniques for medical LCDs, such as Sub-Pixel Modulation and Error Diffusion, are evaluated based on E-MSE and the validity of the proposed technique is ensured objectively.

This paper presents a novel layout approach using dual supply voltage technique. In Placing and Routing (P&R) phase, conventional approaches for dual supply voltages need to separate low supply voltage cells from high voltage ones. Consequently its layout tends to be complex compared with single supply voltage layout. Our layout approach uses cells having two supply voltage rails. Making these cells is difficult in bulk due to increase in area by n-well isolation or in delay by negative body bias caused by sharing n-well. On the other hand, making cells with two supply voltage rails is easy in body-tied PD-SOI owing to trench isolation of each body of transistor. Since our approach for dual supply voltages offers freedom for placement as much as conventional ones for single supply voltage, exsting P&R tools can be used without special operation. Simulation results with MCNC circuits and adders show that our approach reduces power by 23% and 25%, respectively, showing almost the same delay with single supply voltage layout.

This paper presents an image super-resolution technique using a convolutional neural network (CNN) and multi-task learning for multiple image categories. The image categories include natural, manga, and text images. Their features differ from each other. However, several CNNs for super-resolution are trained with a single category. If the input image category is different from that of the training images, the performance of super-resolution is degraded. There are two possible solutions to manage multi-categories with conventional CNNs. The first involves the preparation of the CNNs for every category. This solution, however, requires a category classifier to select an appropriate CNN. The second is to learn all categories with a single CNN. In this solution, the CNN cannot optimize its internal behavior for each category. Therefore, this paper presents a super-resolution CNN architecture for multiple image categories. The proposed CNN has two parallel outputs for a high-resolution image and a category label. The main CNN for the high-resolution image is a normal three convolutional layer-architecture, and the sub neural network for the category label is branched out from its middle layer and consists of two fully-connected layers. This architecture can simultaneously learn the high-resolution image and its category using multi-task learning. The category information is used for optimizing the super-resolution. In an applied setting, the proposed CNN can automatically estimate the input image category and change the internal behavior. Experimental results of 2× image magnification have shown that the average peak signal-to-noise ratio for the proposed method is approximately 0.22 dB higher than that for the conventional super-resolution with no difference in processing time and parameters. We have ensured that the proposed method is useful when the input image category is varying.

This paper presents a fully integrated 32-MHz relaxation oscillator (ROSC) capable of sub-1-µs start-up time operation for low-power intermittent VLSI systems. The proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-µm CMOS demonstrated that the ROSC generates a stable clock frequency of 32.6 MHz within 1-µs start-up time. Measured line regulation and temperature coefficient were ±0.69% and ±0.38%, respectively.

This paper presents an error diagnosis technique for incremental synthesis, called EXLLS (Extended X-algorithm for LUT-based circuit model based on Location sets to rectify Subcircuits), which rectifies five or more functional errors in the whole circuit based on location sets to rectify subcircuits. Conventional error diagnosis technique, called EXLIT, tries to rectify five or more functional errors based on incremental rectification for subcircuits. However, the solution depends on the selection and the order of modifications on subcircuits, which increases the number of locations to be changed. To overcome this problem, we propose EXLLS based on location sets to rectify subcircuits, which obtains two or more solutions by separating i) extraction of location sets to be rectified, and ii) rectification for the whole circuit based on the location sets. Thereby EXLLS can rectify five or more errors with fewer locations to change. Experimental results have shown that EXLLS reduces increase in the number of locations to be rectified with conventional technique by 90.1%.

In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (VDD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM design boosting the word line (WL) voltage higher than VDD in short transition time without dual power supply rails. Simulation results have shown improvement in both the delay time and power consumption.