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[Author] Kosuke SHIOKI(2hit)

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  • An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits

    Kosuke SHIOKI  Narumi OKADA  Toshiro ISHIHARA  Tetsuya HIROSE  Nobutaka KUROKI  Masahiro NUMA  

     
    PAPER-Logic Synthesis, Test and Verfication

      Vol:
    E92-A No:12
      Page(s):
    3136-3142

    This paper presents an error diagnosis technique for incremental synthesis, called EXLLS (Extended X-algorithm for LUT-based circuit model based on Location sets to rectify Subcircuits), which rectifies five or more functional errors in the whole circuit based on location sets to rectify subcircuits. Conventional error diagnosis technique, called EXLIT, tries to rectify five or more functional errors based on incremental rectification for subcircuits. However, the solution depends on the selection and the order of modifications on subcircuits, which increases the number of locations to be changed. To overcome this problem, we propose EXLLS based on location sets to rectify subcircuits, which obtains two or more solutions by separating i) extraction of location sets to be rectified, and ii) rectification for the whole circuit based on the location sets. Thereby EXLLS can rectify five or more errors with fewer locations to change. Experimental results have shown that EXLLS reduces increase in the number of locations to be rectified with conventional technique by 90.1%.

  • An Error Diagnosis Technique Based on Clustering of Elements

    Kosuke SHIOKI  Narumi OKADA  Kosuke WATANABE  Tetsuya HIROSE  Nobutaka KUROKI  Masahiro NUMA  

     
    PAPER-Logic Synthesis, Test and Verification

      Vol:
    E93-A No:12
      Page(s):
    2490-2496

    In this paper, we propose an error diagnosis technique based on clustering LUT elements to shorten the processing time. By grouping some elements as a cluster, our technique reduces the number of elements to be considered, which is effective to shorten the processing time for screening error location sets. First, the proposed technique partitions the circuit into FFR (fanout-free region) called cluster, which is a subcircuit composed of LUT elements without fanout. After screening the set of clusters including error locations, this technique screens error location sets composed of elements in the remaining set of clusters, where corrections should be made. Experimental results with benchmark circuits have shown that our technique shortens the processing time to 1/170 in the best case, and rectifies circuits including 6 errors which cannot be rectified by the conventional technique.