IEICE TRANSACTIONS on Fundamentals
An Error Diagnosis Technique Based on Clustering of Elements
Summary :
In this paper, we propose an error diagnosis technique based on clustering LUT elements to shorten the processing time. By grouping some elements as a cluster, our technique reduces the number of elements to be considered, which is effective to shorten the processing time for screening error location sets. First, the proposed technique partitions the circuit into FFR (fanout-free region) called cluster, which is a subcircuit composed of LUT elements without fanout. After screening the set of clusters including error locations, this technique screens error location sets composed of elements in the remaining set of clusters, where corrections should be made. Experimental results with benchmark circuits have shown that our technique shortens the processing time to 1/170 in the best case, and rectifies circuits including 6 errors which cannot be rectified by the conventional technique.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.12 pp.2490-2496
- Publication Date
- 2010/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.2490
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verification
Authors
Keyword
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Kosuke SHIOKI, Narumi OKADA, Kosuke WATANABE, Tetsuya HIROSE, Nobutaka KUROKI, Masahiro NUMA, "An Error Diagnosis Technique Based on Clustering of Elements" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2490-2496, December 2010, doi: 10.1587/transfun.E93.A.2490.
Abstract: In this paper, we propose an error diagnosis technique based on clustering LUT elements to shorten the processing time. By grouping some elements as a cluster, our technique reduces the number of elements to be considered, which is effective to shorten the processing time for screening error location sets. First, the proposed technique partitions the circuit into FFR (fanout-free region) called cluster, which is a subcircuit composed of LUT elements without fanout. After screening the set of clusters including error locations, this technique screens error location sets composed of elements in the remaining set of clusters, where corrections should be made. Experimental results with benchmark circuits have shown that our technique shortens the processing time to 1/170 in the best case, and rectifies circuits including 6 errors which cannot be rectified by the conventional technique.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2490/_p
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@ARTICLE{e93-a_12_2490,
author={Kosuke SHIOKI, Narumi OKADA, Kosuke WATANABE, Tetsuya HIROSE, Nobutaka KUROKI, Masahiro NUMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Error Diagnosis Technique Based on Clustering of Elements},
year={2010},
volume={E93-A},
number={12},
pages={2490-2496},
abstract={In this paper, we propose an error diagnosis technique based on clustering LUT elements to shorten the processing time. By grouping some elements as a cluster, our technique reduces the number of elements to be considered, which is effective to shorten the processing time for screening error location sets. First, the proposed technique partitions the circuit into FFR (fanout-free region) called cluster, which is a subcircuit composed of LUT elements without fanout. After screening the set of clusters including error locations, this technique screens error location sets composed of elements in the remaining set of clusters, where corrections should be made. Experimental results with benchmark circuits have shown that our technique shortens the processing time to 1/170 in the best case, and rectifies circuits including 6 errors which cannot be rectified by the conventional technique.},
keywords={},
doi={10.1587/transfun.E93.A.2490},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - An Error Diagnosis Technique Based on Clustering of Elements
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2490
EP - 2496
AU - Kosuke SHIOKI
AU - Narumi OKADA
AU - Kosuke WATANABE
AU - Tetsuya HIROSE
AU - Nobutaka KUROKI
AU - Masahiro NUMA
PY - 2010
DO - 10.1587/transfun.E93.A.2490
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - In this paper, we propose an error diagnosis technique based on clustering LUT elements to shorten the processing time. By grouping some elements as a cluster, our technique reduces the number of elements to be considered, which is effective to shorten the processing time for screening error location sets. First, the proposed technique partitions the circuit into FFR (fanout-free region) called cluster, which is a subcircuit composed of LUT elements without fanout. After screening the set of clusters including error locations, this technique screens error location sets composed of elements in the remaining set of clusters, where corrections should be made. Experimental results with benchmark circuits have shown that our technique shortens the processing time to 1/170 in the best case, and rectifies circuits including 6 errors which cannot be rectified by the conventional technique.
ER -
English
