Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation

Masaaki IIJIMA; Masayuki KITAMURA; Masahiro NUMA; Akira TADA; Takashi IPPOSHI; Shigeto MAEGAWA

doi:10.1093/ietele/e90-c.4.666

Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation

Masaaki IIJIMA, Masayuki KITAMURA, Masahiro NUMA, Akira TADA, Takashi IPPOSHI, Shigeto MAEGAWA

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In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (V_DD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM design boosting the word line (WL) voltage higher than V_DD in short transition time without dual power supply rails. Simulation results have shown improvement in both the delay time and power consumption.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.666-674

Publication Date: 2007/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.4.666

Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)

Category: Digital

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Masaaki IIJIMA, Masayuki KITAMURA, Masahiro NUMA, Akira TADA, Takashi IPPOSHI, Shigeto MAEGAWA, "Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 4, pp. 666-674, April 2007, doi: 10.1093/ietele/e90-c.4.666.
Abstract: In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (V_DD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM design boosting the word line (WL) voltage higher than V_DD in short transition time without dual power supply rails. Simulation results have shown improvement in both the delay time and power consumption.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.666/_p

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@ARTICLE{e90-c_4_666,
author={Masaaki IIJIMA, Masayuki KITAMURA, Masahiro NUMA, Akira TADA, Takashi IPPOSHI, Shigeto MAEGAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation},
year={2007},
volume={E90-C},
number={4},
pages={666-674},
abstract={In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (V_DD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM design boosting the word line (WL) voltage higher than V_DD in short transition time without dual power supply rails. Simulation results have shown improvement in both the delay time and power consumption.},
keywords={},
doi={10.1093/ietele/e90-c.4.666},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation
T2 - IEICE TRANSACTIONS on Electronics
SP - 666
EP - 674
AU - Masaaki IIJIMA
AU - Masayuki KITAMURA
AU - Masahiro NUMA
AU - Akira TADA
AU - Takashi IPPOSHI
AU - Shigeto MAEGAWA
PY - 2007
DO - 10.1093/ietele/e90-c.4.666
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (V_DD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM design boosting the word line (WL) voltage higher than V_DD in short transition time without dual power supply rails. Simulation results have shown improvement in both the delay time and power consumption.
ER -