A novel high speed 4-2 compressor using static and pass-transistor logic, has been designed in a 0.35 µm CMOS technology. In order to reduce gate level delay and increase the speed, some changes are performed in truth table of conventional 4-2 compressor which leaded to the simplification of logic function for all parameters. Therefore, power dissipation is decreased. In addition, because of similar paths from all inputs to the outputs, the delays are the same. So there will be no need for extra buffers in low latency paths to equalize the delays.

In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.

In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (VDD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM design boosting the word line (WL) voltage higher than VDD in short transition time without dual power supply rails. Simulation results have shown improvement in both the delay time and power consumption.

A pass-transistor logic is enhanced with a bootstrap configuration for sub-1 V operation at high speed and low power. The bootstrap configuration drives the output to full swing, which accelerates the signal transition and cuts off the short-circuit current of subsequent CMOS logic gates. The asynchronous or synchronous timing sequence of the input (drain) and the control (gate) signals ensures bootstrap operation. A 1-b arithmetic logic unit (ALU) and an EXNOR gate built with the bootstrap pass-transistor logic outperforms those built with other types of pass-transistor logic. An experimental 16-b pass-transistor adder operates down to 0.4 V with a delay time of 4.2 ns and a power dissipation of 2.8 µ W/MHz at 0.5 V.

Binary Decision Diagrams (BDDs) are graph representation of Boolean functions. In particular, Ordered BDDs (OBDDs) are useful in many situations, because they provide canonical representation and they are manipulated efficiently. BDD packages which automatically generate OBDDs have been developed, and they are now widely used in logic design area, including formal verification and logic synthesis. Synthesis of pass-transistor circuits is one of successful applications of such BDD packages. Pass-transistor circuits are generated from BDDs by mapping each node to a selector which consists of two or four pass transistors. If circuits are generated from smaller BDDs, generated circuits have smaller number of transistors and hence save chip area and power consumption. In this paper, more generic BDDs which have no restrictions in variable ordering and variable appearance count on its paths are called Generic BDDs (GBDDs), and an algorithm for generating GBDDs is proposed for the purpose of synthesis of pass-transistor circuits. The proposed algorithm consists of two steps. At the first step, parse trees (PTs) for given Boolean formulas are generated, where a PT is a directed tree representation of Boolean formula(s) and it consists of literal nodes and operation nodes. In this step, our algorithm attempts to reduce the number of literal nodes of PTs. At the second step, a GBDD is generated for the PTs using Concatenation Method, where Concatenation Method generates a GBDD by connecting GBDDs vertically. In this step, our algorithm attempts to share isomorphic subgraphs. In experiments on ISCAS'89 and MCNC benchmark circuits, our program successfully generated 32 GBDDs out of 680 single-output functions and 4 GBDDs out of 49 multi-output functions whose sizes are smaller than OBDDs. GBDD size is reduced by 23.1% in the best case compared with OBDD.

In several design methods for Pass-transistor Logic (PTL) circuits, Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper, we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.

In this paper, a novel pass-transistor logic with an efficient level restoration circuit, named Power Saved Pass-transistor Logic (PSPL), is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of PSPL, a 5454-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth Encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13. 5 ns in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. Furthermore, a sequential circuit of a low power 7-bit serial counter is designed and fabricated in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. The measured operating speed was 250 MHz.

After analyzing the limitations of the traditional description of CMOS circuits at the gate level, this paper introduces the notions of switching and signal variables for describing the switching states of MOS transistors and signals in CMOS circuits, respectively. Two connection operations for describing the interaction between MOS transistors and signals and a new description for MOS circuits at the switch level are presented. This new description can be used to express the functional relationship between inputs and the output at the switch level. It can also be used to describe the circuit structure composed of MOS switches. The new description can be effectively used to design both CMOS circuits and nMOS pass transistor circuits.

Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was discussed in previous work [1]. RPL combines advantages of both the compact size of CPL and the full voltage-swing of DPL, and gives reasonably high performance concerning both speed and power consumption. In this paper, the application and design technique of RPL on larger logic circuits and systems are reported. Parallel adders and Booth multipliers with different sizes and structures are used as examples to evaluate the functionality of the RPL gates and full adder. In addition, there is less signal skew in RPL circuits than in conventional CPL circuits when an arrangement of single-rail to dual-rail signal conversion is performed. And, RPL is found to be useful in design of high speed and high density parallel adders and multipliers.

Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was developed. The technique can be applied to basic logic gates, full adders, multiplier units, and more complicated arithmetic logics like Conditional Carry Select (CCS) circuit. The magnitude of propagation delay time of RPL is smaller than the conventional CPL(Complementary Pass-transistor Logic), or DPL (Double Pass-transistor Logic). Low power consumption can also be achieved by reduced number of transistors and metal interconnections. Simulation and layout data also proved that RPL is advantageous over existing dual-rail logics while considering speed, power consumption and layout area.

In arithmetic units multiplication is a very important operation. It is a common approach to use the modified Booth's algorithm to reduce the number of partial products in a multiplication and speed it up. In this letter we show two circuits that fuse the usually separate functions of generating the partial products and selecting them. The circuits designed in DPL (Double Pass-transistor Logic) are bigger in MOS transistors, but are faster and, function at higher frequencies than a typical CMOS implementation. One of our circuits also has lower power consumption.

This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSIs now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing: 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static cicuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.

This report describes 4-2 compressors composed of Complementary Pass-Transistor Logic (CPL). We will show that circuit designs of the 4-2 compressors can be optimized for high speed and small size using only exclusive-OR's and multiplexers. According to a circuit simulation with 0.8µm CMOS device parameters, the maximum propagation delay and the average power consumption per unit adder are 1.32 ns and 11.6 pJ, respectively.